forked from M-Labs/artiq
rtio: fix/cleanup parameters
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07d3f87c51
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@ -89,6 +89,7 @@ class Core(Module, AutoCSR):
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outputs = SED(channels, glbl_fine_ts_width, "async",
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quash_channels=quash_channels,
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lane_count=lane_count, fifo_depth=fifo_depth,
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interface=self.cri)
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self.submodules += outputs
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self.comb += outputs.coarse_timestamp.eq(coarse_ts)
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@ -13,7 +13,7 @@ __all__ = ["SED"]
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class SED(Module):
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def __init__(self, channels, glbl_fine_ts_width, mode,
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lane_count=8, fifo_depth=128, enable_spread=True,
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quash_channels=[], interface=None, report_buffer_space=False):
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quash_channels=[], report_buffer_space=False, interface=None):
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if mode == "sync":
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lane_dist_cdr = lambda x: x
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fifos_cdr = lambda x: x
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