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test: fix test_dma

This commit is contained in:
Sebastien Bourdeauducq 2018-03-04 23:19:06 +08:00
parent 928d5dc9b3
commit d747d74cb3
1 changed files with 1 additions and 1 deletions
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2
artiq/gateware/test/rtio/test_dma.py
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@ -57,7 +57,7 @@ def do_dma(dut, address):
yield yield
while ((yield from dut.enable.read())): while ((yield from dut.enable.read())):
yield yield
error = yield from dut.cri_master.underflow.read() error = yield from dut.cri_master.error.read()
if error & 1: if error & 1:
raise RTIOUnderflow raise RTIOUnderflow
if error & 2: if error & 2: