forked from M-Labs/artiq
sayma: add EEMs to Master
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@ -13,8 +13,9 @@ from misoc.interconnect.csr import *
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from misoc.targets.sayma_amc import BaseSoC, MiniSoC
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from artiq.gateware.amp import AMPSoC
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from artiq.gateware import serwb
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from artiq.gateware import remote_csr
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from artiq.gateware import eem
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from artiq.gateware import fmcdio_vhdci_eem
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from artiq.gateware import serwb, remote_csr
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from artiq.gateware import rtio
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from artiq.gateware import jesd204_tools
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from artiq.gateware.rtio.phy import ttl_simple, sawg
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@ -450,7 +451,7 @@ class Master(MiniSoC, AMPSoC):
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk, gth.rxoutclk)
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rtio_channels = []
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self.rtio_channels = rtio_channels = []
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for i in range(4):
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phy = ttl_simple.Output(platform.request("user_led", i))
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self.submodules += phy
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@ -466,6 +467,20 @@ class Master(MiniSoC, AMPSoC):
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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platform.add_extension(fmcdio_vhdci_eem.io)
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platform.add_connectors(fmcdio_vhdci_eem.connectors)
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fmcdio_dirctl = platform.request("fmcdio_dirctl")
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for s in fmcdio_dirctl.clk, fmcdio_dirctl.ser, fmcdio_dirctl.latch:
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phy = ttl_simple.Output(s)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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eem.Urukul.add_std(self, 1, 0, ttl_simple.Output,
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iostandard="LVDS")
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eem.DIO.add_std(self, 2, ttl_simple.Output, ttl_simple.Output,
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iostandard="LVDS")
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eem.Zotino.add_std(self, 3, ttl_simple.Output,
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iostandard="LVDS")
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self.config["HAS_RTIO_LOG"] = None
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self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
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rtio_channels.append(rtio.LogChannel())
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