forked from M-Labs/artiq
wrpll: collector code modifications from Weida
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@ -1,5 +1,6 @@
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from migen import *
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from migen.genlib.cdc import PulseSynchronizer, MultiReg
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from migen.genlib.fsm import FSM
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from misoc.interconnect.csr import *
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@ -117,9 +118,38 @@ class Collector(Module):
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# # #
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last_tag_main = Signal(N)
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fsm = FSM()
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self.submodules += fsm
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tag_collector = Signal(N)
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fsm.act("IDLE",
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If(self.tag_main_update & self.tag_helper_update,
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NextValue(tag_collector, 0),
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NextState("IDLE")
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).Elif(self.tag_main_update,
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NextValue(tag_collector, self.tag_main),
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NextState("WAITHELPER")
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).Elif(self.tag_helper_update,
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NextValue(tag_collector, -self.tag_helper),
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NextState("WAITMAIN")
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)
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)
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fsm.act("WAITHELPER",
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If(self.tag_helper_update,
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NextValue(tag_collector, tag_collector - self.tag_helper),
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NextState("IDLE")
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)
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)
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fsm.act("WAITMAIN",
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If(self.tag_main_update,
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NextValue(tag_collector, tag_collector + self.tag_main),
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NextState("IDLE")
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)
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)
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self.sync += [
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If(self.tag_main_update, last_tag_main.eq(self.tag_main)),
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self.output_update.eq(self.tag_helper_update),
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self.output.eq(last_tag_main - self.tag_helper)
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self.output_update.eq(0),
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If(self.tag_helper_update,
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self.output_update.eq(1),
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self.output.eq(tag_collector)
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)
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]
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