forked from M-Labs/artiq
phaser: update sawg tests
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51f23feeac
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d678bb3fb6
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@ -36,8 +36,8 @@ class ParallelDDS(Module):
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self.comb += [
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xy_delay.i.eq(Cat(self.i.x, self.i.y)),
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z_delay.i.eq(Cat([zi[-widths.p:]
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for zi in accu.o.payload.flatten()])),
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z_delay.i.eq(Cat(zi[-widths.p:]
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for zi in accu.o.payload.flatten())),
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eqh(accu.i.p, self.i.p),
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accu.i.f.eq(self.i.f),
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accu.i.clr.eq(self.i.clr),
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@ -45,7 +45,7 @@ class ParallelDDS(Module):
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self.i.ack.eq(accu.i.ack),
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accu.o.ack.eq(1),
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[Cat(c.xi, c.yi).eq(xy_delay.o) for c in cordic],
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Cat([c.zi for c in cordic]).eq(z_delay.o),
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Cat(c.zi for c in cordic).eq(z_delay.o),
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]
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@ -71,8 +71,15 @@ class SplineParallelDUC(ParallelDDS):
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f.o.ack.eq(self.ce),
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eqh(self.i.f, f.o.a0),
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eqh(self.i.p, p.o.a0),
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self.i.clr.eq(self.clr),
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self.i.stb.eq(p.o.stb & f.o.stb),
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self.i.stb.eq(p.o.stb | f.o.stb),
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]
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assert p.latency == 1
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self.sync += [
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self.i.clr.eq(0),
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If(p.i.stb,
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self.i.clr.eq(self.clr),
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),
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]
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@ -94,20 +101,24 @@ class SplineParallelDDS(SplineParallelDUC):
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class Config(Module):
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def __init__(self):
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self.clr = Signal(4)
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self.iq_en = Signal(2)
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limit = [Signal((16, True)) for i in range(2*2)]
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self.limit = [limit[i:i + 2] for i in range(0, len(limit), 2)]
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self.i = Endpoint([("addr", bits_for(len(limit) + 2)), ("data", 16)])
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def __init__(self, width):
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self.clr = Signal(4, reset=0b1111)
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self.iq_en = Signal(2, reset=0b01)
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self.limit = [[Signal((width, True), reset=-(1 << width - 1)),
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Signal((width, True), reset=(1 << width - 1) - 1)]
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for i in range(2)]
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self.i = Endpoint([("addr", bits_for(4 + 2*len(self.limit))),
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("data", 16)])
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self.ce = Signal()
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###
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div = Signal(16)
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div = Signal(16, reset=0)
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n = Signal.like(div)
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pad = Signal()
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reg = Array([Cat(self.clr, self.iq_en), Cat(div, n)] + self.limit)
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reg = Array([Cat(div, n), self.clr, self.iq_en, pad] +
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sum(self.limit, []))
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self.comb += [
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self.i.ack.eq(1),
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@ -130,22 +141,22 @@ class Channel(Module, SatAddMixin):
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orders = _Orders(a=4, f=2, p=1)
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if widths is None:
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widths = _Widths(t=width, a=orders.a*width, p=orders.p*width,
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f=3*width + (orders.f - 1)*width)
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f=(orders.f + 2)*width)
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cfg = Config()
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a1 = SplineParallelDDS(widths, orders)
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a2 = SplineParallelDDS(widths, orders)
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b = SplineParallelDUC(widths, orders, parallelism=parallelism,
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a_delay=-a1.latency)
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self.submodules.a1 = a1 = SplineParallelDDS(widths, orders)
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self.submodules.a2 = a2 = SplineParallelDDS(widths, orders)
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self.submodules.b = b = SplineParallelDUC(
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widths, orders, parallelism=parallelism, a_delay=-a1.latency)
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cfg = Config(widths.a)
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u = Spline(width=widths.a, order=orders.a)
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du = Delay(widths.a, a1.latency + b.latency - u.latency)
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self.submodules += cfg, a1, a2, b, u, du
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self.cfg = cfg.i
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self.submodules += cfg, u, du
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self.u = u.tri(widths.t)
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self.i = [self.cfg, self.u, a1.a, a1.f, a1.p, a2.a, a2.f, a2.p, b.f, b.p]
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self.y_in = [Signal((width, True)) for i in range(b.parallelism)]
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self.y_out = b.yo
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self.o = [Signal((width, True)) for i in range(b.parallelism)]
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self.i = [cfg.i, self.u, a1.a, a1.f, a1.p, a2.a, a2.f, a2.p, b.f, b.p]
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self.i_names = "cfg u a1 f1 p1 a2 f2 p2 f0 p0".split()
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self.i_named = dict(zip(self.i_names, self.i))
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self.y_in = [Signal((width, True)) for i in range(parallelism)]
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self.o = [Signal((width, True)) for i in range(parallelism)]
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self.widths = widths
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self.orders = orders
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self.parallelism = parallelism
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@ -167,10 +178,11 @@ class Channel(Module, SatAddMixin):
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# wire up outputs and q_{i,o} exchange
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for o, x, y in zip(self.o, b.xo, self.y_in):
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self.sync += [
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o.eq(self.sat_add([du.o,
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o.eq(self.sat_add([
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du.o,
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Mux(cfg.iq_en[0], x, 0),
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Mux(cfg.iq_en[1], y, 0)])),
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]
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def connect_q_from(self, buddy):
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self.comb += Cat(self.y_in).eq(Cat(buddy.y_out))
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def connect_y(self, buddy):
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self.comb += Cat(buddy.y_in).eq(Cat(self.b.yo))
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@ -16,14 +16,12 @@ class Channel(_ChannelPHY):
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_ChannelPHY.__init__(self, *args, **kwargs)
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self.phys = []
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for i in self.i:
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rl = rtlink.Interface(rtlink.OInterface(
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min(32, len(i.payload)))) # TODO: test/expand
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rl = rtlink.Interface(rtlink.OInterface(len(i.payload)))
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self.comb += [
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i.stb.eq(rl.o.stb),
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rl.o.busy.eq(~i.ack),
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Cat(i.payload.flatten()).eq(rl.o.data),
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i.payload.raw_bits().eq(rl.o.data),
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]
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# no probes, overrides
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# TODO probes, overrides
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self.phys.append(_Phy(rl, [], []))
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self.phys_names = dict(zip("cfg f0 p0 a1 f1 p1 a2 f2 p2".split(),
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self.phys))
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self.phys_named = dict(zip(self.i_names, self.phys))
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@ -3,23 +3,25 @@ import numpy as np
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from migen import *
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from migen.fhdl.verilog import convert
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from artiq.gateware.dsp.sawg import DDSFast
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from artiq.gateware.dsp import sawg
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from .tools import xfer
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def _test_gen_dds(dut, o):
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yield from xfer(dut,
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a=dict(a=10),
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p=dict(p=0),
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f=dict(f=1 << 8),
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a=dict(a0=10),
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p=dict(a0=0),
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f=dict(a0=1),
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)
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for i in range(256//dut.parallelism):
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yield
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o.append((yield from [(yield _) for _ in dut.o]))
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o.append((yield from [(yield _) for _ in dut.xo]))
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def _test_channel():
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dut = DDSFast(width=8, parallelism=2)
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widths = sawg._Widths(t=8, a=4*8, p=8, f=16)
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orders = sawg._Orders(a=4, p=1, f=2)
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dut = sawg.SplineParallelDDS(widths, orders, parallelism=2)
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if False:
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print(convert(dut))
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@ -1,25 +1,32 @@
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import numpy as np
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from operator import or_
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from migen import *
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from migen.fhdl.verilog import convert
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from artiq.gateware.rtio.phy.sawg import Channel
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from .tools import xfer, szip
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from .tools import rtio_xfer
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def rtio_xfer(dut, **kwargs):
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yield from szip(*(
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xfer(dut.phys_names[k].rtlink, o={"data": v})
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for k, v in kwargs.items()))
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def pack_tri(port, *v):
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r = 0
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w = 0
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for vi, p in zip(v, port.payload.flatten()):
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w += len(p)
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r |= int(vi*(1 << w))
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return r
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def gen_rtio(dut):
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width = dut.width
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yield
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yield from rtio_xfer(
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dut, a=int(.1 * (1 << width)),
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f=int(.01234567 * (1 << 2*width)),
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p=0)
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dut,
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a1=pack_tri(dut.a1.a, .1),
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f0=pack_tri(dut.b.f, .01234567),
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f1=pack_tri(dut.a1.f, .01234567),
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a2=pack_tri(dut.a1.a, .05),
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f2=pack_tri(dut.a1.f, .00534567),
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)
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def gen_log(dut, o, n):
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@ -28,10 +35,12 @@ def gen_log(dut, o, n):
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for i in range(n):
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yield
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o.append((yield from [(yield _) for _ in dut.o]))
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#o.append([(yield dut.a1.xo[0])])
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def _test_channel():
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width = 16
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dut = ClockDomainsRenamer({"rio_phy": "sys"})(
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Channel(width=width, parallelism=4)
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)
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@ -43,8 +52,8 @@ def _test_channel():
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o = []
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run_simulation(
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dut,
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[gen_rtio(dut), gen_log(dut, o, 256 * 2)],
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) # vcd_name="dds.vcd")
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[gen_rtio(dut), gen_log(dut, o, 128)],
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vcd_name="dds.vcd")
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o = np.array(o)/(1 << (width - 1))
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o = o.ravel()
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np.savez_compressed("dds.npz", o=o)
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@ -41,3 +41,9 @@ def szip(*iters):
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val = (yield None)
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for it in active:
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active[it] = val
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def rtio_xfer(dut, **kwargs):
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yield from szip(*(
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xfer(dut.phys_named[k].rtlink, o={"data": v})
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for k, v in kwargs.items()))
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