From d6704d30e9380272064b49c1111a29eb1b6afa45 Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Tue, 30 May 2023 11:49:13 +0800
Subject: [PATCH] fix IBUFDS_GTE2 parameters

---
 artiq/gateware/drtio/transceiver/gtx_7series.py |  7 +++----
 artiq/gateware/targets/kasli.py                 | 10 ++++++++--
 artiq/gateware/targets/sayma_rtm.py             |  5 ++++-
 3 files changed, 15 insertions(+), 7 deletions(-)

diff --git a/artiq/gateware/drtio/transceiver/gtx_7series.py b/artiq/gateware/drtio/transceiver/gtx_7series.py
index 3d96971ca..e32a8f289 100644
--- a/artiq/gateware/drtio/transceiver/gtx_7series.py
+++ b/artiq/gateware/drtio/transceiver/gtx_7series.py
@@ -296,10 +296,9 @@ class GTX(Module, TransceiverInterface):
             i_I=clock_pads.p,
             i_IB=clock_pads.n,
             o_O=refclk,
-            p_CLKCM_CFG="0b1",
-            p_CLKRCV_TRST="0b1",
-            p_CLKSWING_CFG="0b11"
-        )
+            p_CLKCM_CFG="TRUE",
+            p_CLKRCV_TRST="TRUE",
+            p_CLKSWING_CFG=3)
 
         rtio_tx_clk = Signal()
         channel_interfaces = []
diff --git a/artiq/gateware/targets/kasli.py b/artiq/gateware/targets/kasli.py
index dd5580602..5084b8922 100755
--- a/artiq/gateware/targets/kasli.py
+++ b/artiq/gateware/targets/kasli.py
@@ -418,7 +418,10 @@ class MasterBase(MiniSoC, AMPSoC):
         self.specials += Instance("IBUFDS_GTE2",
             i_CEB=self.disable_cdr_clk_ibuf,
             i_I=cdr_clk_clean.p, i_IB=cdr_clk_clean.n,
-            o_O=cdr_clk_clean_buf)
+            o_O=cdr_clk_clean_buf,
+            p_CLKCM_CFG="TRUE",
+            p_CLKRCV_TRST="TRUE",
+            p_CLKSWING_CFG=3)
         # Note precisely the rules Xilinx made up:
         # refclksel=0b001 GTREFCLK0 selected
         # refclksel=0b010 GTREFCLK1 selected
@@ -476,7 +479,10 @@ class SatelliteBase(BaseSoC):
         self.specials += Instance("IBUFDS_GTE2",
             i_CEB=disable_cdr_clk_ibuf,
             i_I=cdr_clk_clean.p, i_IB=cdr_clk_clean.n,
-            o_O=cdr_clk_clean_buf)
+            o_O=cdr_clk_clean_buf,
+            p_CLKCM_CFG="TRUE",
+            p_CLKRCV_TRST="TRUE",
+            p_CLKSWING_CFG=3)
         qpll_drtio_settings = QPLLSettings(
             refclksel=0b001,
             fbdiv=4,
diff --git a/artiq/gateware/targets/sayma_rtm.py b/artiq/gateware/targets/sayma_rtm.py
index 9d72ea04e..824e2e9ec 100755
--- a/artiq/gateware/targets/sayma_rtm.py
+++ b/artiq/gateware/targets/sayma_rtm.py
@@ -50,7 +50,10 @@ class _SatelliteBase(BaseSoC):
         self.specials += Instance("IBUFDS_GTE2",
             i_CEB=disable_cdrclkc_ibuf,
             i_I=cdrclkc_clkout.p, i_IB=cdrclkc_clkout.n,
-            o_O=cdrclkc_clkout_buf)
+            o_O=cdrclkc_clkout_buf,
+            p_CLKCM_CFG="TRUE",
+            p_CLKRCV_TRST="TRUE",
+            p_CLKSWING_CFG=3)
         qpll_drtio_settings = QPLLSettings(
             refclksel=0b001,
             fbdiv=4,