forked from M-Labs/artiq
suservo: fix cnv_b diff
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@ -76,6 +76,8 @@ class ADC(Module, DiffMixin):
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self.sync += pads.sck_en.eq(sck_en) # ODDR delay
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self.specials += io.DDROutput(0, sck_en,
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self._diff(pads, "sck", output=True))
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cnv_b = Signal()
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self.comb += self._diff(pads, "cnv_b", output=True).eq(cnv_b)
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self.submodules.fsm = fsm = FSM("IDLE")
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fsm.act("IDLE",
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self.done.eq(1),
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@ -86,7 +88,7 @@ class ADC(Module, DiffMixin):
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)
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fsm.act("CNVH",
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count_load.eq(p.t_conv - 2), # account for sck ODDR delay
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pads.cnv_b.eq(1),
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cnv_b.eq(1),
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If(count_done,
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NextState("CONV")
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)
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