forked from M-Labs/artiq
cri: add routing table support
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df61b85988
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@ -2,6 +2,7 @@
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from migen import *
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from migen.genlib.record import *
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from migen.genlib.cdc import MultiReg
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from misoc.interconnect.csr import *
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@ -109,8 +110,8 @@ class KernelInitiator(Module, AutoCSR):
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self.sync += If(self.counter_update.re, self.counter.status.eq(tsc.full_ts_cri))
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class CRIDecoder(Module):
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def __init__(self, slaves=2, master=None):
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class CRIDecoder(Module, AutoCSR):
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def __init__(self, slaves=2, master=None, mode="async", enable_routing=False):
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if isinstance(slaves, int):
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slaves = [Interface() for _ in range(slaves)]
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if master is None:
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@ -118,10 +119,41 @@ class CRIDecoder(Module):
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self.slaves = slaves
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self.master = master
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slave_bits = bits_for(len(slaves)-1)
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if enable_routing:
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self.routing_destination = CSRStorage(8)
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self.routing_hop = CSR(slave_bits)
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# # #
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selected = Signal(8, reset_less=True)
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self.sync += selected.eq(self.master.chan_sel[16:])
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# routing
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selected = Signal(slave_bits)
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if enable_routing:
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self.specials.routing_table = Memory(slave_bits, 8)
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rtp_csr = self.routing_table.get_port(write_capable=True)
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self.specials += rtp_csr
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self.comb += [
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rtp_csr.adr.eq(self.routing_destination.storage),
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rtp_csr.dat_w.eq(self.routing_hop.r),
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rtp_csr.we.eq(self.routing_hop.re),
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self.routing_hop.w.eq(rtp_csr.dat_r)
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]
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if mode == "async":
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rtp_decoder = self.routing_table.get_port()
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elif mode == "sync":
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rtp_decoder = self.routing_table.get_port(clock_domain="rtio")
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else:
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raise ValueError
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self.specials += rtp_decoder
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self.comb += [
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rtp_decoder.adr.eq(self.master.chan_sel[16:]),
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selected.eq(rtp_decoder.dat_r)
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]
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else:
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self.sync += selected.eq(self.master.chan_sel[16:])
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# master -> slave
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for n, slave in enumerate(slaves):
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@ -141,7 +173,7 @@ class CRIDecoder(Module):
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class CRISwitch(Module, AutoCSR):
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def __init__(self, masters=2, slave=None):
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def __init__(self, masters=2, slave=None, mode="async"):
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if isinstance(masters, int):
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masters = [Interface() for _ in range(masters)]
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if slave is None:
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@ -153,6 +185,15 @@ class CRISwitch(Module, AutoCSR):
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# # #
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if mode == "async":
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selected = self.selected.storage
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elif mode == "sync":
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self.selected.storage.attr.add("no_retiming")
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selected = Signal.like(self.selected.storage)
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self.specials += MultiReg(self.selected.storage, selected, "rtio")
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else:
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raise ValueError
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if len(masters) == 1:
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self.comb += masters[0].connect(slave)
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else:
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@ -160,7 +201,7 @@ class CRISwitch(Module, AutoCSR):
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for name, size, direction in layout:
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if direction == DIR_M_TO_S:
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choices = Array(getattr(m, name) for m in masters)
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self.comb += getattr(slave, name).eq(choices[self.selected.storage])
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self.comb += getattr(slave, name).eq(choices[selected])
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# connect slave->master signals
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for name, size, direction in layout:
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@ -170,11 +211,12 @@ class CRISwitch(Module, AutoCSR):
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dest = getattr(m, name)
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self.comb += dest.eq(source)
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class CRIInterconnectShared(Module):
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def __init__(self, masters=2, slaves=2):
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def __init__(self, masters=2, slaves=2, mode="async", enable_routing=False):
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shared = Interface()
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self.submodules.switch = CRISwitch(masters, shared)
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self.submodules.decoder = CRIDecoder(slaves, shared)
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self.submodules.switch = CRISwitch(masters, shared, mode)
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self.submodules.decoder = CRIDecoder(slaves, shared, mode, enable_routing)
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def get_csrs(self):
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return self.switch.get_csrs()
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return self.switch.get_csrs() + self.decoder.get_csrs()
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