forked from M-Labs/artiq
drtio: synchronizer MMCM
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@ -2,6 +2,7 @@ from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from misoc.cores.code_8b10b import Encoder, Decoder
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from misoc.interconnect.csr import *
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from artiq.gateware.drtio.transceiver.gtx_7series_init import *
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@ -175,7 +176,7 @@ class GTX_1000BASE_BX10(Module):
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]
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class RXSynchronizer(Module):
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class RXSynchronizer(Module, AutoCSR):
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"""Delays the data received in the rtio_rx by a configurable amount
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so that it meets s/h in the rtio domain, and recapture it in the rtio
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domain. This has fixed latency.
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@ -188,9 +189,42 @@ class RXSynchronizer(Module):
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Xilinx scriptures (when existent) and should be constant for a given design
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placement.
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"""
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def __init__(self):
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self.cd_rtio_delayed = ClockDomain()
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# TODO
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def __init__(self, rtio_clk_freq):
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self.phase_shift = CSR()
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self.phase_shift_done = CSRStatus()
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self.cd_rtio_delayed = ClockDomain(reset_less=True)
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mmcm_output = Signal()
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mmcm_fb = Signal()
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# maximize VCO frequency to maximize phase shift resolution
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mmcm_mult = 1200e9//rtio_clk_freq
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self.specials += [
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Instance("MMCME2_ADV",
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p_CLKIN1_PERIOD=1e9/rtio_clk_freq,
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i_CLKIN1=ClockSignal("rtio_rx"),
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i_CLKINSEL=1, # yes, 1=CLKIN1 0=CLKIN2
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p_CLKFBOUT_MULT_F=mmcm_mult,
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p_CLKOUT0_DIVIDE_F=mmcm_mult,
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p_DIVCLK_DIVIDE=1,
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# According to Xilinx, there is no guarantee of input/output
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# phase relationship when using internal feedback. We assume
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# here that the input/ouput skew is constant to save BUFGs.
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o_CLKFBOUT=mmcm_fb,
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i_CLKFBIN=mmcm_fb,
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p_CLKOUT0_USE_FINE_PS="TRUE",
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o_CLKOUT0=mmcm_output,
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i_PSCLK=ClockSignal(),
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i_PSEN=self.phase_shift.re,
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i_PSINCDEC=self.phase_shift.r,
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o_PSDONE=self.phase_shift_done.status,
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),
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Instance("BUFR", i_I=mmcm_output, o_O=self.cd_rtio_delayed.clk)
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]
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def sync(self, signal):
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delayed = Signal.like(signal, related=signal)
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