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ad9910: fix pll timeout loop 

Signed-off-by: Robert Jördens <rj@quartiq.de>
This commit is contained in:
Robert Jördens 2018-11-02 12:22:42 +00:00
parent 4269d5ad5c
commit d3ad2b7633
1 changed files with 11 additions and 9 deletions
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6
artiq/coredevice/ad9910.py
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@ -166,17 +166,19 @@ class AD9910:
self.cpld.io_update.pulse(1*us)
if blind:
delay(100*ms)
return
else:
# Wait for PLL lock, up to 100 ms
for i in range(100):
sta = self.cpld.sta_read()
lock = urukul_sta_pll_lock(sta)
delay(1*ms)
if lock & (1 << self.chip_select - 4):
return
break
if i >= 100 - 1:
raise ValueError("PLL lock timeout")
if self.sync_delay_seed >= 0:
self.tune_sync_delay(self.sync_delay_seed)
delay(1*ms)
@kernel
def power_down(self, bits=0b1111):