forked from M-Labs/artiq
kasli: fix SDRAM read delay reset/wrap issue. Closes #1149
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@ -242,6 +242,12 @@ mod ddr {
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ddrphy::dly_sel_write(1 << (DQS_SIGNAL_COUNT - n - 1));
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ddrphy::rdly_dq_rst_write(1);
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#[cfg(soc_platform = "kasli")]
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{
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for _ in 0..3 {
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ddrphy::rdly_dq_bitslip_write(1);
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}
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}
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for _ in 0..DDRPHY_MAX_DELAY {
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let mut working = true;
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@ -327,6 +333,12 @@ mod ddr {
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let mut max_seen_valid = 0;
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ddrphy::rdly_dq_rst_write(1);
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#[cfg(soc_platform = "kasli")]
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{
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for _ in 0..3 {
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ddrphy::rdly_dq_bitslip_write(1);
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}
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}
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for delay in 0..DDRPHY_MAX_DELAY {
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let mut valid = true;
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@ -384,6 +396,12 @@ mod ddr {
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// Set delay to the middle
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ddrphy::rdly_dq_rst_write(1);
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#[cfg(soc_platform = "kasli")]
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{
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for _ in 0..3 {
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ddrphy::rdly_dq_bitslip_write(1);
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}
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}
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for _ in 0..mean_delay {
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ddrphy::rdly_dq_inc_write(1);
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}
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@ -15,7 +15,7 @@ requirements:
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- python >=3.5.3,<3.6
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- setuptools 33.1.1
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- migen 0.8 py35_0+git2d62c0c
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- misoc 0.11 py35_31+git5ce139dd
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- misoc 0.11 py35_33+git128750aa
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- jesd204b 0.10
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- microscope
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- binutils-or1k-linux >=2.27
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