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README_PHASER: update
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ARTIQ Phaser
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============
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This ARTIQ branch contains a proof-of-concept design of a GHz-datarate multichannel direct digital synthesizer (DDS) compatible with ARTIQ's RTIO channels.
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In later developments this proof-of-concept can be expanded to provide a two-tone output with spline modulation and multi-DAC synchronization.
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Ultimately it will be the basis for the ARTIQ Sayma Smart Arbitrary Waveform Generator project. See https://github.com/m-labs/sayma and https://github.com/m-labs/artiq-hardware.
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This ARTIQ branch contains a proof-of-concept design of a GHz-datarate, multi-channel, interpolating, multi-tone, direct digital synthesizer (DDS) compatible with ARTIQ's RTIO channels.
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Ultimately it will be the basis for the ARTIQ Sayma Smart Arbitrary Waveform Generator project. See https://github.com/m-labs/sinara and https://github.com/m-labs/artiq-hardware.
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*Features*:
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* up to 4 channels
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* up to 500 MHz data rate per channel (KC705 limitation)
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* up to 8x interpolation to 2.4 GHz DAC sample rate
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* Real-time control over amplitude, frequency, phase of each channel through ARTIQ RTIO commands
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* Real-time sample-coherent control over amplitude, frequency, phase of each channel through ARTIQ RTIO commands
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* Full configurability of the AD9154 and AD9516 through SPI with ARTIQ kernel support
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* All SPI registers and register bits exposed as human readable names
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* Parametrized JESD204B core (also capable of operation with eight lanes)
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@ -18,12 +17,11 @@ Ultimately it will be the basis for the ARTIQ Sayma Smart Arbitrary Waveform Gen
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The hardware required to use the ARTIQ phaser branch is a KC705 with an AD9154-FMC-EBZ plugged into the HPC connector and a low-noise sample rate reference clock.
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This work was supported by the Army Research Lab.
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This work was supported by the Army Research Lab and the University of Maryland.
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The code that was developed for this project is located in several repositories:
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* In ARTIQ, the SAWG and Phaser code: https://github.com/m-labs/artiq/compare/phaser
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* The CORDIC core has been reused from the PDQ2 gateware https://github.com/m-labs/pdq2
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* In ARTIQ, the SAWG and Phaser code: https://github.com/m-labs/artiq/compare/phaser2
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* The Migen/MiSoC JESD204B core: https://github.com/m-labs/jesd204b
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@ -32,7 +30,7 @@ Installation
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These installation instructions are a short form of those in the ARTIQ manual.
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Please refer to and follow the ARTIQ manual for more details:
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https://m-labs.hk/artiq/manual-release-2/index.html
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https://m-labs.hk/artiq/manual-master/index.html
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* Set up a new conda environment and activate it.
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* Install the standard ARTIQ runtime/install dependencies.
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@ -42,22 +40,20 @@ https://m-labs.hk/artiq/manual-release-2/index.html
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* Install the standard ARTIQ build dependencies.
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They are all available as conda packages in m-labs/main or m-labs/dev for linux-64:
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- migen =0.4
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- misoc =0.4
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- llvm-or1k =3.8
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- migen
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- misoc
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- jesd204b
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- llvm-or1k
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- rust-core-or1k
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- cargo
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- binutils-or1k-linux >=2.27
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- binutils-or1k-linux
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* Install a recent version of Vivado (tested and developed with 2016.2).
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* Checkout the ARTIQ phaser branch and the JESD204B core: ::
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* Do a checkout of the ARTIQ phaser2 branch: ::
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mkdir ~/src
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cd ~/src
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git clone --recursive -b phaser https://github.com/m-labs/artiq.git
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git clone https://github.com/m-labs/jesd204b.git
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cd jesd204b
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python setup.py develop
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git clone --recursive -b phaser2 https://github.com/m-labs/artiq.git
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cd ../artiq
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python setup.py develop
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@ -74,11 +70,13 @@ Setup
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* Compile the ARTIQ Phaser bitstream, bios, and runtime (c.f. ARTIQ manual): ::
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python -m artiq.gateware.targets.phaser --toolchain vivado
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python -m artiq.gateware.targets.phaser
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* Generate an ARTIQ configuration flash image with MAC and IP address (see the
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documentation for ``artiq_mkfs``). Name it ``phaser_config.bin``.
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* Run the following OpenOCD command to flash the ARTIQ phaser design: ::
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openocd -f board/kc705.cfg -c "init; jtagspi_init 0 bscan_spi_xc7k325t.bit; jtagspi_program misoc_phaser_kc705/gateware/top.bin 0x000000; jtagspi_program misoc_phaser_kc705/software/bios/bios.bin 0xaf0000; jtagspi_program misoc_phaser_kc705/software/runtime/runtime.fbi 0xb00000; xc7_program xc7.tap; exit"
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openocd -f board/kc705.cfg -c "init; jtagspi_init 0 bscan_spi_xc7k325t.bit; jtagspi_program misoc_phaser_kc705/gateware/top.bin 0x000000; jtagspi_program misoc_phaser_kc705/software/bios/bios.bin 0xaf0000; jtagspi_program misoc_phaser_kc705/software/runtime/runtime.fbi 0xb00000;jtagspi_program phaser_config.bin 0xb80000; xc7_program xc7.tap; exit"
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The proxy bitstream ``bscan_spi_xc7k325t.bit`` can be found at https://github.com/jordens/bscan_spi_bitstreams or in any ARTIQ conda package for the KC705.
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See the source code of ``artiq_flash.py`` from ARTIQ for more details.
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@ -91,7 +89,7 @@ Setup
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* Refer to the ARTIQ documentation to configure an IP address and other settings for the transmitter device.
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If the board was running stock ARTIQ before, the settings will be kept.
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* A 300 MHz clock of roughly 10 dBm (0.2 to 3.4 V peak-to-peak into 50 Ohm) must be connected to the AD9154-FMC-EBZ J1.
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The external RTIO clock, DAC deviceclock, FPGA deviceclock, and SYSREF are derived from this signal.
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The external RTIO clock, DAC deviceclock, FPGA deviceclock, and SYSREF are derived from this signal. There is no internal RTIO clock.
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* An example device database, several status and test scripts are provided in ``artiq/examples/phaser/``. ::
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cd artiq/examples/phaser
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@ -109,9 +107,9 @@ Usage
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* Run ``artiq_run repository/ad9154_test_status.py`` to retrieve and print several status registers from the AD9154 DAC.
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* Run ``artiq_run repository/ad9154_test_prbs.py`` to test the JESD204B PHY layer for bit errors. Reboot the core device afterwards.
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* Run ``artiq_run repository/ad9154_test_stpl.py`` to executes a JESD204B short transport layer test.
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* Run ``artiq_run repository/sawg.py`` for an example that sets up amplitudes, frequencies, and phases on all four DDS channels.
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* Run ``artiq_run repository/demo.py`` for an example that exercises several different use cases of synchronized phase, amplitude, and frequency updates.
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for an example that exercises several different use cases of synchronized phase, amplitude, and frequency updates.
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* Run ``artiq_run repository/demo_2tone.py`` for an example that emits a shaped two-tone pulse.
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* Implement your own experiments using the SAWG channels.
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* Verify clock stability between the sample rate reference clock and the DAC outputs.
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* Changes to the AD9154 configuration can also be performed at runtime in experiments.
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