forked from M-Labs/artiq
parent
1bb09f9ca6
commit
d22eefc13e
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@ -156,15 +156,9 @@ def obj_sequential():
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def fn_watchdog():
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def fn_watchdog():
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return types.TBuiltinFunction("watchdog")
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return types.TBuiltinFunction("watchdog")
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def fn_now():
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return types.TBuiltinFunction("now")
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def fn_delay():
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def fn_delay():
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return types.TBuiltinFunction("delay")
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return types.TBuiltinFunction("delay")
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def fn_at():
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return types.TBuiltinFunction("at")
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def fn_now_mu():
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def fn_now_mu():
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return types.TBuiltinFunction("now_mu")
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return types.TBuiltinFunction("now_mu")
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@ -36,9 +36,7 @@ def globals():
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"watchdog": builtins.fn_watchdog(),
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"watchdog": builtins.fn_watchdog(),
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# ARTIQ time management functions
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# ARTIQ time management functions
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"now": builtins.fn_now(),
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"delay": builtins.fn_delay(),
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"delay": builtins.fn_delay(),
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"at": builtins.fn_at(),
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"now_mu": builtins.fn_now_mu(),
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"now_mu": builtins.fn_now_mu(),
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"delay_mu": builtins.fn_delay_mu(),
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"delay_mu": builtins.fn_delay_mu(),
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"at_mu": builtins.fn_at_mu(),
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"at_mu": builtins.fn_at_mu(),
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@ -1671,19 +1671,12 @@ class ARTIQIRGenerator(algorithm.Visitor):
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self.polymorphic_print([self.visit(arg) for arg in args],
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self.polymorphic_print([self.visit(arg) for arg in args],
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separator=" ", suffix="\n\x1D", as_rtio=True)
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separator=" ", suffix="\n\x1D", as_rtio=True)
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return ir.Constant(None, builtins.TNone())
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return ir.Constant(None, builtins.TNone())
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elif types.is_builtin(typ, "now"):
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elif types.is_builtin(typ, "delay"):
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if len(node.args) == 0 and len(node.keywords) == 0:
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now_mu = self.append(ir.Builtin("now_mu", [], builtins.TInt64()))
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now_mu_float = self.append(ir.Coerce(now_mu, builtins.TFloat()))
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return self.append(ir.Arith(ast.Mult(loc=None), now_mu_float, self.ref_period))
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else:
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assert False
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elif types.is_builtin(typ, "delay") or types.is_builtin(typ, "at"):
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if len(node.args) == 1 and len(node.keywords) == 0:
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if len(node.args) == 1 and len(node.keywords) == 0:
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arg = self.visit(node.args[0])
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arg = self.visit(node.args[0])
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arg_mu_float = self.append(ir.Arith(ast.Div(loc=None), arg, self.ref_period))
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arg_mu_float = self.append(ir.Arith(ast.Div(loc=None), arg, self.ref_period))
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arg_mu = self.append(ir.Coerce(arg_mu_float, builtins.TInt64()))
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arg_mu = self.append(ir.Coerce(arg_mu_float, builtins.TInt64()))
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return self.append(ir.Builtin(typ.name + "_mu", [arg_mu], builtins.TNone()))
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return self.append(ir.Builtin("delay_mu", [arg_mu], builtins.TNone()))
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else:
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else:
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assert False
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assert False
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elif types.is_builtin(typ, "now_mu") or types.is_builtin(typ, "delay_mu") \
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elif types.is_builtin(typ, "now_mu") or types.is_builtin(typ, "delay_mu") \
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@ -1,10 +1,8 @@
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# RUN: %python -m artiq.compiler.testbench.jit %s
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# RUN: %python -m artiq.compiler.testbench.jit %s
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# REQUIRES: time
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# REQUIRES: time
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assert now() == 0.0
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assert now_mu() == 0
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delay(100.0)
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delay(100.0)
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assert now() == 100.0
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assert now_mu() == 100000000
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at(12345.0)
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at_mu(12345000000)
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assert now() == 12345.0
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assert now_mu() == 12345000000
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assert now_mu() == 12345000000
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