forked from M-Labs/artiq
drtio: rt_packets → rt_packet
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6b7c781ff2
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d1b9f9d737
@ -33,7 +33,7 @@ class _CSRs(AutoCSR):
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class RTController(Module):
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def __init__(self, rt_packets, channel_count, fine_ts_width):
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def __init__(self, rt_packet, channel_count, fine_ts_width):
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self.csrs = _CSRs()
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self.cri = cri.Interface()
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self.comb += self.cri.arb_gnt.eq(1)
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@ -52,25 +52,25 @@ class RTController(Module):
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self.csrs.tsc_correction.storage.attr.add("no_retiming")
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self.specials += MultiReg(self.csrs.tsc_correction.storage, tsc_correction)
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self.comb += [
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rt_packets.tsc_value.eq(
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rt_packet.tsc_value.eq(
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self.counter.value_rtio + tsc_correction),
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self.csrs.set_time.w.eq(rt_packets.set_time_stb)
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self.csrs.set_time.w.eq(rt_packet.set_time_stb)
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]
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self.sync += [
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If(rt_packets.set_time_ack, rt_packets.set_time_stb.eq(0)),
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If(self.csrs.set_time.re, rt_packets.set_time_stb.eq(1))
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If(rt_packet.set_time_ack, rt_packet.set_time_stb.eq(0)),
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If(self.csrs.set_time.re, rt_packet.set_time_stb.eq(1))
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]
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# reset
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self.sync += [
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If(rt_packets.reset_ack, rt_packets.reset_stb.eq(0)),
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If(rt_packet.reset_ack, rt_packet.reset_stb.eq(0)),
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If(self.csrs.reset.re,
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rt_packets.reset_stb.eq(1),
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rt_packets.reset_phy.eq(0)
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rt_packet.reset_stb.eq(1),
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rt_packet.reset_phy.eq(0)
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),
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If(self.csrs.reset_phy.re,
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rt_packets.reset_stb.eq(1),
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rt_packets.reset_phy.eq(1)
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rt_packet.reset_stb.eq(1),
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rt_packet.reset_phy.eq(1)
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),
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]
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@ -95,18 +95,18 @@ class RTController(Module):
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self.specials += last_timestamps_mem, last_timestamps
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# common packet fields
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rt_packets_fifo_request = Signal()
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rt_packet_fifo_request = Signal()
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self.comb += [
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fifo_spaces.adr.eq(chan_sel),
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last_timestamps.adr.eq(chan_sel),
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last_timestamps.dat_w.eq(self.cri.timestamp),
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rt_packets.sr_channel.eq(chan_sel),
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rt_packets.sr_address.eq(self.cri.o_address),
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rt_packets.sr_data.eq(self.cri.o_data),
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rt_packets.sr_timestamp.eq(self.cri.timestamp),
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If(rt_packets_fifo_request,
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rt_packets.sr_notwrite.eq(1),
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rt_packets.sr_address.eq(0)
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rt_packet.sr_channel.eq(chan_sel),
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rt_packet.sr_address.eq(self.cri.o_address),
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rt_packet.sr_data.eq(self.cri.o_data),
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rt_packet.sr_timestamp.eq(self.cri.timestamp),
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If(rt_packet_fifo_request,
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rt_packet.sr_notwrite.eq(1),
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rt_packet.sr_address.eq(0)
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)
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]
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@ -159,8 +159,8 @@ class RTController(Module):
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)
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fsm.act("WRITE",
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status_wait.eq(1),
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rt_packets.sr_stb.eq(1),
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If(rt_packets.sr_ack,
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rt_packet.sr_stb.eq(1),
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If(rt_packet.sr_ack,
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fifo_spaces.we.eq(1),
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fifo_spaces.dat_w.eq(fifo_spaces.dat_r - 1),
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last_timestamps.we.eq(1),
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@ -173,20 +173,20 @@ class RTController(Module):
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)
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fsm.act("GET_FIFO_SPACE",
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status_wait.eq(1),
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rt_packets_fifo_request.eq(1),
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rt_packets.sr_stb.eq(1),
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rt_packets.fifo_space_not_ack.eq(1),
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If(rt_packets.sr_ack,
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rt_packet_fifo_request.eq(1),
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rt_packet.sr_stb.eq(1),
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rt_packet.fifo_space_not_ack.eq(1),
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If(rt_packet.sr_ack,
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NextState("GET_FIFO_SPACE_REPLY")
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)
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)
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fsm.act("GET_FIFO_SPACE_REPLY",
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status_wait.eq(1),
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fifo_spaces.dat_w.eq(rt_packets.fifo_space),
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fifo_spaces.dat_w.eq(rt_packet.fifo_space),
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fifo_spaces.we.eq(1),
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rt_packets.fifo_space_not_ack.eq(1),
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If(rt_packets.fifo_space_not,
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If(rt_packets.fifo_space != 0,
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rt_packet.fifo_space_not_ack.eq(1),
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If(rt_packet.fifo_space_not,
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If(rt_packet.fifo_space != 0,
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NextState("IDLE")
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).Else(
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NextState("GET_FIFO_SPACE")
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@ -211,7 +211,7 @@ class RTController(Module):
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)
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]
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self.sync += \
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If((rt_packets.sr_stb & rt_packets.sr_ack & rt_packets_fifo_request),
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If((rt_packet.sr_stb & rt_packet.sr_ack & rt_packet_fifo_request),
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self.csrs.o_dbg_fifo_space_req_cnt.status.eq(
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self.csrs.o_dbg_fifo_space_req_cnt.status + 1)
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)
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@ -221,7 +221,7 @@ class RTController(Module):
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class RTManager(Module, AutoCSR):
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def __init__(self, rt_packets):
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def __init__(self, rt_packet):
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self.request_echo = CSR()
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self.packet_err_present = CSR()
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@ -233,20 +233,20 @@ class RTManager(Module, AutoCSR):
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# # #
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self.comb += self.request_echo.w.eq(rt_packets.echo_stb)
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self.comb += self.request_echo.w.eq(rt_packet.echo_stb)
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self.sync += [
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If(rt_packets.echo_ack, rt_packets.echo_stb.eq(0)),
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If(self.request_echo.re, rt_packets.echo_stb.eq(1))
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If(rt_packet.echo_ack, rt_packet.echo_stb.eq(0)),
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If(self.request_echo.re, rt_packet.echo_stb.eq(1))
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]
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self.comb += [
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self.packet_err_present.w.eq(rt_packets.error_not),
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rt_packets.error_not_ack.eq(self.packet_err_present.re),
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self.packet_err_code.status.eq(rt_packets.error_code)
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self.packet_err_present.w.eq(rt_packet.error_not),
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rt_packet.error_not_ack.eq(self.packet_err_present.re),
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self.packet_err_code.status.eq(rt_packet.error_code)
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]
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self.sync += \
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If(self.update_packet_cnt.re,
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self.packet_cnt_tx.status.eq(rt_packets.packet_cnt_tx),
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self.packet_cnt_rx.status.eq(rt_packets.packet_cnt_rx)
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self.packet_cnt_tx.status.eq(rt_packet.packet_cnt_tx),
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self.packet_cnt_rx.status.eq(rt_packet.packet_cnt_rx)
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)
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