srenblad
/
artiq
forked from M-Labs/artiq
1
0
Fork 0
Code Pull Requests Activity

sayma_amc_standalone: connect sawg to jesd again

This commit is contained in:
Robert Jördens 2017-11-19 14:36:20 +01:00
parent dfdd2dd9e6
commit d1a7c1c3a1
1 changed files with 3 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
artiq/gateware/targets/sayma_amc_standalone.py
View File

@ -92,18 +92,11 @@ class AD9154(Module, AutoCSR):
def __init__(self, platform, sys_crg, jesd_crg, dac): def __init__(self, platform, sys_crg, jesd_crg, dac):
self.submodules.jesd = AD9154JESD(platform, sys_crg, jesd_crg, dac) self.submodules.jesd = AD9154JESD(platform, sys_crg, jesd_crg, dac)
self.sawgs = [sawg.Channel(width=16, parallelism=8) for i in range(8)] self.sawgs = [sawg.Channel(width=16, parallelism=4) for i in range(4)]
self.submodules += self.sawgs self.submodules += self.sawgs
for i in range(len(self.sawgs)): for conv, ch in zip(self.jesd.core.sink.flatten(), self.sawgs):
self.sawgs[i].connect_y(self.sawgs[i ^ 1]) self.sync.jesd += conv.eq(Cat(ch.o))
# FIXME
#for conv, ch in zip(
# self.jesd.core0.sink.flatten() +
# self.jesd.core1.sink.flatten(),
# self.sawgs):
# self.sync.jesd += conv.eq(Cat(ch.o))
class SaymaAMCStandalone(MiniSoC, AMPSoC): class SaymaAMCStandalone(MiniSoC, AMPSoC):