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kasli: v2 clocking WIP, remove SFP LEDs from RTIO

This commit is contained in:
Sebastien Bourdeauducq 2020-04-23 23:02:18 +08:00
parent 9bc43b2dbf
commit d19f28fa84
1 changed files with 10 additions and 6 deletions
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16
artiq/gateware/targets/kasli.py
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@ -32,7 +32,10 @@ class _RTIOCRG(Module, AutoCSR):
self.clock_domains.cd_rtio = ClockDomain() self.clock_domains.cd_rtio = ClockDomain()
self.clock_domains.cd_rtiox4 = ClockDomain(reset_less=True) self.clock_domains.cd_rtiox4 = ClockDomain(reset_less=True)
clk_synth = platform.request("si5324_clkout_fabric") if platform.hw_rev == "v2.0":
clk_synth = platform.request("cdr_clk_clean_fabric")
else:
clk_synth = platform.request("si5324_clkout_fabric")
clk_synth_se = Signal() clk_synth_se = Signal()
platform.add_period_constraint(clk_synth.p, 8.0) platform.add_period_constraint(clk_synth.p, 8.0)
self.specials += [ self.specials += [
@ -174,11 +177,12 @@ class Tester(StandaloneBase):
eem.Sampler.add_std(self, 3, 2, ttl_serdes_7series.Output_8X) eem.Sampler.add_std(self, 3, 2, ttl_serdes_7series.Output_8X)
eem.Zotino.add_std(self, 4, ttl_serdes_7series.Output_8X) eem.Zotino.add_std(self, 4, ttl_serdes_7series.Output_8X)
for i in (1, 2): if hw_rev in ("v1.0", "v1.1"):
sfp_ctl = self.platform.request("sfp_ctl", i) for i in (1, 2):
phy = ttl_simple.Output(sfp_ctl.led) sfp_ctl = self.platform.request("sfp_ctl", i)
self.submodules += phy phy = ttl_simple.Output(sfp_ctl.led)
self.rtio_channels.append(rtio.Channel.from_phy(phy)) self.submodules += phy
self.rtio_channels.append(rtio.Channel.from_phy(phy))
self.config["HAS_RTIO_LOG"] = None self.config["HAS_RTIO_LOG"] = None
self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels) self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)