srenblad
/
artiq
forked from M-Labs/artiq
1
0
Fork 0
Code Pull Requests Activity

sawg: absolute phase updates

This commit is contained in:
Robert Jördens 2016-10-14 12:11:39 +02:00
parent 9b43f09c1d
commit d16068dd9b
1 changed files with 3 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
artiq/gateware/dsp/sawg.py
View File

@ -37,8 +37,10 @@ class DDSFast(Module):
If(self.f.stb,
eqh(q.i.f, self.f.f)
),
q.i.clr.eq(0),
If(self.p.stb,
eqh(q.i.p, self.p.p)
eqh(q.i.p, self.p.p),
q.i.clr.eq(1)
),
q.i.stb.eq(self.f.stb | self.p.stb),
]
@ -47,7 +49,6 @@ class DDSFast(Module):
self.f.ack.eq(1),
self.p.ack.eq(1),
q.o.ack.eq(1),
q.i.clr.eq(0),
]
c = []