forked from M-Labs/artiq
phaser: fix frequency comment
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@ -415,7 +415,7 @@ class _PhaserCRG(Module, AutoCSR):
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# Warning: CLKINSEL=0 means CLKIN2 is selected
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i_CLKINSEL=~self._clock_sel.storage,
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# VCO @ 1GHz when using 125MHz input
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# VCO @ 1GHz when using 250MHz input
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p_CLKFBOUT_MULT=8, p_DIVCLK_DIVIDE=2,
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i_CLKFBIN=self.cd_rtio.clk,
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i_RST=self._pll_reset.storage,
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