forked from M-Labs/artiq
phaser: fix README
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@ -9,26 +9,26 @@ The hardware required is a KC705 with an AD9154-FMC-EBZ plugged into the HPC con
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Features:
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* 4 channels
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* 500 MHz data rate per channel (KC705 limitation)
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* 4x interpolation to 2 GHz DAC sample rate
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* Real-time control over amplitude, frequency, phase through ARTIQ RTIO
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channels
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* Full configurability of the AD9154 and AD9516 through SPI with ARTIQ kernel
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support
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* All SPI registers and register bits exposed as human readable names
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* Parametrized JESD204B core (also capable of operation with eight lanes)
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* The code can be reconfigured, e.g. to support 2 channels at 1 GHz datarate or to support 4 channels at 300 MHz data rate, no interpolation, and using mix mode to stress the second and third Nyquist zones (150-300 MHz and 300-450 MHz).
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* 4 channels
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* 500 MHz data rate per channel (KC705 limitation)
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* 4x interpolation to 2 GHz DAC sample rate
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* Real-time control over amplitude, frequency, phase through ARTIQ RTIO
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channels
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* Full configurability of the AD9154 and AD9516 through SPI with ARTIQ kernel
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support
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* All SPI registers and register bits exposed as human readable names
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* Parametrized JESD204B core (also capable of operation with eight lanes)
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* The code can be reconfigured, e.g. to support 2 channels at 1 GHz datarate or to support 4 channels at 300 MHz data rate, no interpolation, and using mix mode to stress the second and third Nyquist zones (150-300 MHz and 300-450 MHz).
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This work was supported by the Army Research Lab.
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The additions and modifications to ARTIQ that were implemented for this project are:
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* In ARTIQ, the SAWG and Phaser code: https://github.com/m-labs/artiq/compare/phaser
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* The CORDIC core has been reused from the PDQ2 gateware
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https://github.com/m-labs/pdq2
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* The Migen/MiSoC JESD204B core: https://github.com/enjoy-digital/litejesd204b
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:
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* In ARTIQ, the SAWG and Phaser code: https://github.com/m-labs/artiq/compare/phaser
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* The CORDIC core has been reused from the PDQ2 gateware
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https://github.com/m-labs/pdq2
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* The Migen/MiSoC JESD204B core: https://github.com/enjoy-digital/litejesd204b
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Installation
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------------
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@ -38,7 +38,8 @@ Please refer to the manual for more details:
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https://m-labs.hk/artiq/manual-release-2/index.html
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* Set up a new conda environment and activate it.
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* Checkout the ARTIQ phaser branch::
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* Checkout the ARTIQ phaser branch: ::
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git clone -b phaser https://github.com/m-labs/artiq.git
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* Install the standard ARTIQ runtime/install dependencies.
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@ -69,10 +70,12 @@ Setup
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- on XP1, between pin 5 and 6 (will keep the PIC in reset)
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- on JP3 (will force output enable on FXLA108)
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* Compile the ARTIQ Phaser bitstream, bios, and runtime (c.f. ARTIQ manual):::
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* Compile the ARTIQ Phaser bitstream, bios, and runtime (c.f. ARTIQ manual): ::
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python -m artiq.gateware.targets.kc705 -H phaser --toolchain vivado
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* Run the following OpenOCD commands to flash the ARTIQ transmitter design:::
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* Run the following OpenOCD commands to flash the ARTIQ transmitter design: ::
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init
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jtagspi_init 0 bscan_spi_xc7k325t.bit
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jtagspi_program misoc_phaser_kc705/gateware/top.bin 0x000000
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