forked from M-Labs/artiq
Add 125 MHz from 80 MHz reference option to rtio clocking
Signed-off-by: Egor Savkin <es@m-labs.hk>
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@ -10,6 +10,7 @@ pub enum RtioClock {
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Int_100,
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Ext0_Bypass,
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Ext0_Synth0_10to125,
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Ext0_Synth0_80to125,
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Ext0_Synth0_100to125,
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Ext0_Synth0_125to125,
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}
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@ -24,6 +25,7 @@ fn get_rtio_clock_cfg() -> RtioClock {
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Ok("ext0_bypass_125") => RtioClock::Ext0_Bypass,
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Ok("ext0_bypass_100") => RtioClock::Ext0_Bypass,
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Ok("ext0_synth0_10to125") => RtioClock::Ext0_Synth0_10to125,
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Ok("ext0_synth0_80to125") => RtioClock::Ext0_Synth0_80to125,
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Ok("ext0_synth0_100to125") => RtioClock::Ext0_Synth0_100to125,
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Ok("ext0_synth0_125to125") => RtioClock::Ext0_Synth0_125to125,
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Ok("i") => {
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@ -44,6 +46,8 @@ fn get_rtio_clock_cfg() -> RtioClock {
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warn!("si5324_ext_ref and ext_ref_frequency compile-time options are deprecated. Please use the rtio_clock coreconfig settings instead.");
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#[cfg(all(rtio_frequency = "125.0", si5324_ext_ref, ext_ref_frequency = "10.0"))]
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return RtioClock::Ext0_Synth0_10to125;
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#[cfg(all(rtio_frequency = "125.0", si5324_ext_ref, ext_ref_frequency = "80.0"))]
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return RtioClock::Ext0_Synth0_80to125;
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#[cfg(all(rtio_frequency = "125.0", si5324_ext_ref, ext_ref_frequency = "100.0"))]
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return RtioClock::Ext0_Synth0_100to125;
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#[cfg(all(rtio_frequency = "125.0", si5324_ext_ref, ext_ref_frequency = "125.0"))]
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@ -110,6 +114,22 @@ fn setup_si5324_pll(cfg: RtioClock) {
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SI5324_EXT_INPUT
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)
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},
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RtioClock::Ext0_Synth0_80to125 => { // 125 MHz output from 80 MHz CLKINx reference, 611 Hz BW
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info!("using 80MHz reference to make 125MHz RTIO clock with PLL");
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(
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si5324::FrequencySettings {
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n1_hs : 4,
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nc1_ls : 10,
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n2_hs : 10,
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n2_ls : 250,
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n31 : 40,
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n32 : 40,
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bwsel : 4,
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crystal_as_ckin2: false
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},
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SI5324_EXT_INPUT
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)
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},
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RtioClock::Ext0_Synth0_100to125 => { // 125MHz output, from 100MHz CLKINx reference, 586 Hz loop bandwidth
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info!("using 100MHz reference to make 125MHz RTIO clock with PLL");
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(
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@ -175,6 +175,7 @@ KC705 in DRTIO variants and Kasli generates the RTIO clock using a PLL locked ei
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* ``int_100`` - internal crystal oscillator using PLL, 100 MHz output,
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* ``int_150`` - internal crystal oscillator using PLL, 150 MHz output,
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* ``ext0_synth0_10to125`` - external 10 MHz reference using PLL, 125 MHz output,
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* ``ext0_synth0_80to125`` - external 80 MHz reference using PLL, 125 MHz output,
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* ``ext0_synth0_100to125`` - external 100 MHz reference using PLL, 125 MHz output,
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* ``ext0_synth0_125to125`` - external 125 MHz reference using PLL, 125 MHz output,
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* ``ext0_bypass``, ``ext0_bypass_125``, ``ext0_bypass_100`` - external clock - with explicit aliases available.
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@ -343,8 +343,9 @@ The KC705 may use either an external clock signal, or its internal clock with ex
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Other options include:
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- ``ext0_synth0_10to125`` - external 10MHz reference clock used by Si5324 to synthesize a 125MHz RTIO clock,
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- ``ext0_synth0_100to125`` - exteral 100MHz reference clock used by Si5324 to synthesize a 125MHz RTIO clock,
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- ``ext0_synth0_125to125`` - exteral 125MHz reference clock used by Si5324 to synthesize a 125MHz RTIO clock,
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- ``ext0_synth0_80to125`` - external 80MHz reference clock used by Si5324 to synthesize a 125MHz RTIO clock,
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- ``ext0_synth0_100to125`` - external 100MHz reference clock used by Si5324 to synthesize a 125MHz RTIO clock,
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- ``ext0_synth0_125to125`` - external 125MHz reference clock used by Si5324 to synthesize a 125MHz RTIO clock,
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- ``int_100`` - internal crystal reference is used by Si5324 to synthesize a 100MHz RTIO clock,
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- ``int_150`` - internal crystal reference is used by Si5324 to synthesize a 150MHz RTIO clock.
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- ``ext0_bypass_125`` and ``ext0_bypass_100`` - explicit aliases for ``ext0_bypass``.
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