srenblad
/
artiq
forked from M-Labs/artiq
1
0
Fork 0
Code Pull Requests Activity

gateware/kc705: add I2C GPIO core for QC2

This commit is contained in:
Sebastien Bourdeauducq 2016-03-03 15:32:10 +08:00
parent a901971e58
commit cfe72c72a2
1 changed files with 14 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
artiq/gateware/targets/kc705.py
View File

@ -291,8 +291,17 @@ class NIST_CLOCK(_NIST_Ions):
class NIST_QC2(_NIST_Ions): class NIST_QC2(_NIST_Ions):
""" """
NIST QC2 hardware, as used in Quantum I and Quantum II, with new backplane NIST QC2 hardware, as used in Quantum I and Quantum II, with new backplane
and 12 DDS channels. Current implementation for single backplane. and 12 DDS channels. Current implementation for single backplane.
""" """
csr_map = {
"i2c": None
}
csr_map.update(_NIST_Ions.csr_map)
mem_map = {
"i2c": 0x30000000 # (shadow @0xb0000000)
}
mem_map.update(_NIST_Ions.mem_map)
def __init__(self, cpu_type="or1k", **kwargs): def __init__(self, cpu_type="or1k", **kwargs):
_NIST_Ions.__init__(self, cpu_type, **kwargs) _NIST_Ions.__init__(self, cpu_type, **kwargs)
@ -341,6 +350,10 @@ class NIST_QC2(_NIST_Ions):
assert self.rtio.fine_ts_width <= 3 assert self.rtio.fine_ts_width <= 3
self.config["DDS_RTIO_CLK_RATIO"] = 24 >> self.rtio.fine_ts_width self.config["DDS_RTIO_CLK_RATIO"] = 24 >> self.rtio.fine_ts_width
i2c = platform.request("i2c")
self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
self.register_kernel_cpu_csrdevice("i2c")
def main(): def main():
parser = argparse.ArgumentParser( parser = argparse.ArgumentParser(