forked from M-Labs/artiq
fir: size hint for pre-adder
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f310274e39
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@ -83,7 +83,10 @@ class FIR(Module):
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else:
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self.comb += o0.eq(o + m)
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assert js[0] - delay >= 0
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self.sync += m.eq(c*reduce(add, [x[j - delay] for j in js]))
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xs = [x[j - delay] for j in js]
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s = Signal((bits_for(len(xs)) - 1 + len(xs[0]), True))
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self.comb += s.eq(sum(xs))
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self.sync += m.eq(c*s)
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# symmetric rounding
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if shift:
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self.comb += o.eq((1 << shift - 1) - 1)
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@ -136,7 +139,10 @@ class ParallelFIR(Module):
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else:
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self.comb += o0.eq(o + m)
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assert js[0] - delay >= 0
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self.sync += m.eq(c*reduce(add, [x[j - delay] for j in js]))
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xs = [x[j - delay] for j in js]
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s = Signal((bits_for(len(xs)) - 1 + len(xs[0]), True))
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self.comb += s.eq(sum(xs))
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self.sync += m.eq(c*s)
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# symmetric rounding
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if shift:
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self.comb += o.eq((1 << shift - 1) - 1)
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