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gateware/targets/sayma_amc_standalone: serwb working, need fixing on AD9154 data mapping

This commit is contained in:
Florent Kermarrec 2017-11-18 18:10:28 +01:00
parent a3383c340c
commit cd83b71d92
1 changed files with 9 additions and 8 deletions
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17
artiq/gateware/targets/sayma_amc_standalone.py
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@ -95,14 +95,15 @@ class AD9154(Module, AutoCSR):
self.sawgs = [sawg.Channel(width=16, parallelism=8) for i in range(8)] self.sawgs = [sawg.Channel(width=16, parallelism=8) for i in range(8)]
self.submodules += self.sawgs self.submodules += self.sawgs
# for i in range(len(self.sawgs)): for i in range(len(self.sawgs)):
# self.sawgs[i].connect_y(self.sawgs[i ^ 1]) self.sawgs[i].connect_y(self.sawgs[i ^ 1])
for conv, ch in zip( # FIXME
self.jesd.core0.sink.flatten() + #for conv, ch in zip(
self.jesd.core1.sink.flatten(), # self.jesd.core0.sink.flatten() +
self.sawgs): # self.jesd.core1.sink.flatten(),
self.sync.jesd += conv.eq(Cat(ch.o)) # self.sawgs):
# self.sync.jesd += conv.eq(Cat(ch.o))
class SaymaAMCStandalone(MiniSoC, AMPSoC): class SaymaAMCStandalone(MiniSoC, AMPSoC):
@ -166,7 +167,7 @@ class SaymaAMCStandalone(MiniSoC, AMPSoC):
serwb_core = serwb.core.SERWBCore(serwb_phy_amc, int(self.clk_freq), mode="slave") serwb_core = serwb.core.SERWBCore(serwb_phy_amc, int(self.clk_freq), mode="slave")
self.submodules += serwb_core self.submodules += serwb_core
self.add_wb_slave(self.mem_map["serwb"], 8192, serwb_core.etherbone.wishbone.bus) self.register_mem("serwb", self.mem_map["serwb"], 8192, serwb_core.etherbone.wishbone.bus)
# RTIO # RTIO
rtio_channels = [] rtio_channels = []