From cd4477864ae9f47d6535ef8d59ab817c151f9abc Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 11 May 2018 23:31:25 +0200 Subject: [PATCH] serwb: fix case when rtm fpga is not loaded, lvds input can be 0 or 1 --- artiq/gateware/serwb/kusphy.py | 3 ++- artiq/gateware/serwb/s7phy.py | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/artiq/gateware/serwb/kusphy.py b/artiq/gateware/serwb/kusphy.py index e0a0bd58b..395c4c0b7 100644 --- a/artiq/gateware/serwb/kusphy.py +++ b/artiq/gateware/serwb/kusphy.py @@ -215,4 +215,5 @@ class KUSSerdes(Module): idle_timer = WaitTimer(32) self.submodules += idle_timer self.comb += idle_timer.wait.eq(1) - self.sync += self.rx_idle.eq(idle_timer.done & (rx_bitslip.o == 0)) + self.sync += self.rx_idle.eq(idle_timer.done & + ((rx_bitslip.o == 0) | (rx_bitslip.o == (2**40-1)))) diff --git a/artiq/gateware/serwb/s7phy.py b/artiq/gateware/serwb/s7phy.py index 967991aea..cc7cc4e30 100644 --- a/artiq/gateware/serwb/s7phy.py +++ b/artiq/gateware/serwb/s7phy.py @@ -226,4 +226,5 @@ class S7Serdes(Module): idle_timer = WaitTimer(32) self.submodules += idle_timer self.comb += idle_timer.wait.eq(1) - self.sync += self.rx_idle.eq(idle_timer.done & (rx_bitslip.o == 0)) + self.sync += self.rx_idle.eq(idle_timer.done & + ((rx_bitslip.o == 0) | (rx_bitslip.o == (2**40-1))))