forked from M-Labs/artiq
rtio: DMA core (untested)
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cd3f68ba76
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from migen import *
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from migen.genlib.record import Record, layout_len
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from migen.genlib.fsm import FSM
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from misoc.interconnect.csr import *
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from misoc.interconnect import stream, wishbone
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from artiq.gateware.rtio import cri
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class WishboneReader(Module):
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def __init__(self, bus=None):
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if bus is None:
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bus = wishbone.Interface
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self.bus = bus
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aw = len(bus.adr)
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dw = len(bus.dat_w)
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self.sink = stream.Endpoint(["address", aw])
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self.source = stream.Endpoint(["data", dw])
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# # #
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bus_stb = Signal()
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data_reg_loaded = Signal()
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self.comb += [
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bus_stb.eq(self.sink.stb & (~data_reg_loaded | self.source.ack)),
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bus.cyc.eq(bus_stb),
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bus.stb.eq(bus_stb),
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bus.adr.eq(self.sink.address),
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self.sink.ack.eq(bus.ack),
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self.source.stb.eq(data_reg_loaded),
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]
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self.sync += [
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If(self.source.ack, data_reg_loaded.eq(0)),
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If(bus.ack,
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data_reg_loaded.eq(1),
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self.source.data.eq(bus.dat_r),
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self.source.eop.eq(self.sink.eop)
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)
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]
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class DMAReader(Module, AutoCSR):
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def __init__(self, membus, enable):
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aw = len(membus.adr)
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data_alignment = log2_int(len(membus.dat_w)//8)
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self.submodules.wb_reader = WishboneReader(membus)
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self.source = self.wb_reader.source
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# All numbers in bytes
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self.base_address = CSRStorage(aw + data_alignment,
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alignment_bits=data_alignment)
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self.last_address = CSRStorage(aw + data_alignment,
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alignment_bits=data_alignment)
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# # #
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enable_r = Signal()
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address = self.wb_reader.sink
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self.sync += [
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enable_r.eq(enable),
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If(enable & ~enable_r,
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address.address.eq(self.base_address.storage),
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address.eop.eq(0),
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address.stb.eq(1)
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),
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If(address.stb & address.ack,
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If(address.eop,
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address.stb.eq(0)
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).Else(
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address.address.eq(address.address + 1),
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If(~enable | (address.address == self.last_address.storage),
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address.eop.eq(1)
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)
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)
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)
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]
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class RawSlicer(Module):
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def __init__(self, in_size, out_size, granularity):
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g = granularity
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self.sink = stream.Endpoint([("data", in_size*g)])
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self.source = Signal(out_size*g)
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self.source_stb = Signal()
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self.source_consume = Signal(max=out_size+1)
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# # #
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# worst-case buffer space required (when loading):
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# <data being shifted out> <new incoming word> <EOP marker>
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buf_size = out_size - 1 + in_size + 1
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buf = Signal(buf_size*g)
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self.comb += self.source.eq(buf[:out_size])
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level = Signal(max=buf_size+1)
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next_level = Signal(max=buf_size+1)
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self.sync += level.eq(next_level)
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self.comb += next_level.eq(level)
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load_buf = Signal()
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shift_buf = Signal()
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self.sync += [
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If(load_buf, Case(level,
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# note how the MSBs of the buffer are set to 0
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# (including the EOP marker position)
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{i: buf[i*g:].eq(self.sink.data)
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for i in range(out_size)})),
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If(shift_buf, buf.eq(buf >> self.source_consume*g))
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]
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fsm = FSM(reset_state="FETCH")
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self.submodules += fsm
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fsm.act("FETCH",
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self.sink.ack.eq(1),
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load_buf.eq(1),
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If(self.sink.stb,
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If(self.sink.eop,
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# insert <granularity> bits of 0 to mark EOP
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next_level.eq(level + in_size + 1)
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).Else(
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next_level.eq(level + in_size)
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)
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),
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If(next_level >= out_size, NextState("OUTPUT"))
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)
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fsm.act("OUTPUT",
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self.source_stb.eq(1),
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shift_buf.eq(1),
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next_level.eq(level - self.source_consume),
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If(next_level < out_size, NextState("FETCH"))
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)
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record_layout = [
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("length", 8), # of whole record (header+data)
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("channel", 24),
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("timestamp", 64),
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("address", 16),
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("data", 512) # variable length
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]
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class RecordConverter(Module):
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def __init__(self, stream_slicer):
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self.source = stream.Endpoint(record_layout)
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hdrlen = layout_len(header_layout) - 512
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record_raw = Record(record_layout)
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self.comb += [
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record_raw.raw_bits().eq(stream_slicer.source),
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record.channel.eq(record_raw.channel),
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record.timestamp.eq(record_raw.timestamp),
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record.address.eq(record_raw.address),
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Case(record_raw.length,
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{hdrlen+i*8: self.cri.o_data.eq(header.data[:])
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for i in range(512//8)}),
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self.source.stb.eq(stream_slicer.source_stb),
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self.source.eop.eq(record_raw.length == 0),
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If(self.source.ack,
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If(record_raw.length == 0,
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stream_slicer.source_consume.eq(1)
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).Else(
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stream_slicer.source_consume.eq(record_raw.length)
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)
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)
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]
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class RecordSlicer(Module):
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def __init__(self, in_size):
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self.submodules.raw_slicer = RawSlicer(
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in_size, layout_len(record_layout)//8, 8)
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self.submodules.record_converter = RecordConverter(self.raw_slicer)
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self.sink = self.raw_slicer.sink
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self.source = self.record_converter.source
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class TimeOffset(Module, AutoCSR):
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def __init__(self):
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self.time_offset = CSRStorage(64)
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self.source = stream.Endpoint(record_layout)
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self.sink = stream.Endpoint(record_layout)
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# # #
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pipe_ce = Signal()
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self.sync += \
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If(pipe_ce,
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self.source.payload.connect(self.sink.payload,
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exclude={"timestamp"}),
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self.source.payload.timestamp.eq(self.sink.payload.timestamp
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+ self.time_offset.storage),
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self.source.stb.eq(self.sink.stb)
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)
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self.comb += [
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self.pipe_ce.eq(self.source.ack | ~self.source.stb),
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self.sink.ack.eq(self.pipe_ce)
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]
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class CRIMaster(Module, AutoCSR):
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def __init__(self):
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self.arb_req = CSRStorage()
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self.arb_gnt = CSRStatus()
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self.error_status = CSRStatus(5) # same encoding as RTIO status
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self.error_underflow_reset = CSR()
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self.error_sequence_error_reset = CSR()
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self.error_collision_reset = CSR()
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self.error_busy_reset = CSR()
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self.error_channel = CSRStatus(24)
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self.error_timestamp = CSRStatus(64)
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self.error_address = CSRStatus(16)
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self.sink = stream.Endpoint(record_layout)
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self.cri = cri.Interface()
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self.busy = Signal()
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# # #
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self.comb += [
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self.cri.arb_req.eq(self.arb_req.storage),
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self.arb_gnt.status.eq(self.cri.arb_gnt)
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]
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error_set = Signal(4)
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for i, rcsr in enumerate([self.error_underflow_reset, self.error_sequence_error_reset,
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self.error_collision_reset, self.error_busy_reset]):
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# bit 0 is RTIO wait and always 0 here
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bit = i + 1
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self.sync += [
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If(error_set[i],
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self.error_status[bit].eq(1),
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self.error_channel.status.eq(self.sink.channel),
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self.error_timestamp.status.eq(self.sink.timestamp),
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self.error_address.status.eq(self.sink.address)
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),
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If(rcsr.re, self.error_status[bit].eq(0))
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]
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self.comb += [
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self.cri.chan_sel.eq(self.sink.channel),
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self.cri.o_timestamp.eq(self.sink.timestamp),
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self.cri.o_address.eq(self.sink.address),
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]
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fsm = FSM(reset_state="IDLE")
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self.submodules += fsm
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fsm.act("IDLE",
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If(self.error_status.status == 0,
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If(self.sink.stb, NextState("WRITE"))
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).Else(
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# discard all data until errors are acked
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self.sink.ack.eq(1)
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)
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)
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fsm.act("WRITE",
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self.busy.eq(1),
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self.cri.cmd.eq(cri.commands["write"]),
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NextState("CHECK_STATE")
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)
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fsm.act("CHECK_STATE",
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self.busy.eq(1),
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If(~self.cri.o_status,
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self.sink.ack.eq(1),
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NextState("IDLE")
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),
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If(self.cri.o_status[1], NextState("UNDERFLOW")),
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If(self.cri.o_status[2], NextState("SEQUENCE_ERROR")),
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If(self.cri.o_status[3], NextState("COLLISION")),
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If(self.cri.o_status[4], NextState("BUSY"))
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)
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for n, name in enumerate(["UNDERFLOW", "SEQUENCE_ERROR",
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"COLLISION", "BUSY"]):
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fsm.act(name,
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self.busy.eq(1),
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error_set.eq(1 << n),
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self.cri.cmd.eq(cri.commands["o_" + name.lower() + "_reset"]),
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self.sink.ack.eq(1),
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NextState("IDLE")
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)
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class DMA(Module):
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def __init__(self, membus):
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# shutdown procedure: set enable to 0, wait until busy=0
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self.enable = CSRStorage()
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self.busy = CSRStatus()
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self.submodules.dma = DMAReader(membus, self.enable.storage)
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self.submodules.slicer = RecordSlicer(len(membus.dat_w))
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self.submodules.time_offset = TimeOffset()
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self.submodules.cri_master = CRIMaster()
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self.comb += [
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self.dma.source.connect(self.slicer.sink),
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self.slicer.source.connect(self.time_offset.sink),
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self.time_offset.source.connect(self.cri_master.sink)
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]
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fsm = FSM(reset_state="IDLE")
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self.submodules += fsm
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fsm.act("IDLE",
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If(self.enable.storage, NextState("FLOWING"))
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)
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fsm.act("FLOWING",
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self.busy.status.eq(1),
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If(self.cri_master.sink.stb & self.cri_master.sink.ack & self.cri_master.sink.eop,
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NextState("WAIT_CRI_MASTER")
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)
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)
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fsm.act("WAIT_CRI_MASTER",
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self.busy.status.eq(1),
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If(~self.cri_master.busy, NextState("IDLE"))
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)
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def get_csrs(self):
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return ([self.enable, self.busy] +
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self.dma.get_csrs() + self.time_offset.get_csrs() +
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self.cri_master.get_csrs())
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