srenblad
/
artiq
forked from M-Labs/artiq
1
0
Fork 0
Code Pull Requests Activity

Reformat.

This commit is contained in:
whitequark 2015-11-20 21:41:44 +08:00
parent d0f86e05d0
commit cc623c13b4
1 changed files with 46 additions and 44 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
artiq/compiler/transforms/interleaver.py
View File

@ -45,7 +45,9 @@ class Interleaver:
postdom_tree = None postdom_tree = None
for insn in func.instructions(): for insn in func.instructions():
if isinstance(insn, ir.Parallel): if not isinstance(insn, ir.Parallel):
continue
# Lazily compute dominators. # Lazily compute dominators.
if postdom_tree is None: if postdom_tree is None:
postdom_tree = domination.PostDominatorTree(func) postdom_tree = domination.PostDominatorTree(func)
@ -83,13 +85,13 @@ class Interleaver:
else: else:
assert False assert False
target_block = source_block
target_time += source_block_delay
new_source_block = postdom_tree.immediate_dominator(source_block) new_source_block = postdom_tree.immediate_dominator(source_block)
assert (new_source_block is not None) assert (new_source_block is not None)
assert delay_free_subgraph(source_block, new_source_block) assert delay_free_subgraph(source_block, new_source_block)
target_block = source_block
target_time += source_block_delay
if new_source_block == interleave_until: if new_source_block == interleave_until:
# We're finished with this branch. # We're finished with this branch.
del source_blocks[index] del source_blocks[index]