forked from M-Labs/artiq
Commit missing parts of 9366a29
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9366a29483
commit
cc45694f5a
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@ -38,15 +38,15 @@ def rtio_get_counter() -> TInt64:
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raise NotImplementedError("syscall not simulated")
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@syscall
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def cache_get(TStr) -> TList(TInt32):
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def cache_get(key: TStr) -> TList(TInt32):
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raise NotImplementedError("syscall not simulated")
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@syscall
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def cache_put(TStr, TList(TInt32)):
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def cache_put(key: TStr, value: TList(TInt32)):
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raise NotImplementedError("syscall not simulated")
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@syscall
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def cache_clear(TStr):
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def cache_clear(key: TStr):
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raise NotImplementedError("syscall not simulated")
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class Core:
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@ -1036,10 +1036,13 @@ static int process_kmsg(struct msg_base *umsg)
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}
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if(!row->borrowed) {
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row->length = request->length;
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row->elements = calloc(row->length, sizeof(int32_t));
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memcpy(row->elements, request->elements,
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sizeof(int32_t) * row->length);
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if(request->length != 0) {
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row->length = request->length;
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row->elements = calloc(row->length, sizeof(int32_t));
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memcpy(row->elements, request->elements,
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sizeof(int32_t) * row->length);
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}
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reply.succeeded = 1;
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} else {
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reply.succeeded = 0;
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