From cb76f9da896d3a7db04eb3ca8f314a8aa18b3113 Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Fri, 29 May 2020 15:59:44 +0800
Subject: [PATCH] metlino: fix CSR collisions

Closes #1425
---
 artiq/gateware/targets/metlino.py | 1 +
 1 file changed, 1 insertion(+)

diff --git a/artiq/gateware/targets/metlino.py b/artiq/gateware/targets/metlino.py
index b9746848a..d1013653c 100755
--- a/artiq/gateware/targets/metlino.py
+++ b/artiq/gateware/targets/metlino.py
@@ -46,6 +46,7 @@ class Master(MiniSoC, AMPSoC):
                          integrated_sram_size=8192,
                          ethmac_nrxslots=4,
                          ethmac_ntxslots=4,
+                         csr_address_width=15,
                          **kwargs)
         AMPSoC.__init__(self)
         add_identifier(self)