From cb5fd08713aa7d64a0c54df752cf1128ce138426 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Wed, 20 Jan 2016 09:38:44 -0500 Subject: [PATCH] targets/kc705: fix e664fe3 --- artiq/gateware/targets/kc705.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/artiq/gateware/targets/kc705.py b/artiq/gateware/targets/kc705.py index 4503c2b73..6cefef172 100755 --- a/artiq/gateware/targets/kc705.py +++ b/artiq/gateware/targets/kc705.py @@ -196,8 +196,6 @@ class NIST_QC1(_NIST_QCx): rtio_channels.append(rtio.Channel.from_phy(phy)) self.config["RTIO_DDS_CHANNEL"] = len(rtio_channels) - assert self.rtio.fine_ts_width <= 3 - self.config["DDS_RTIO_CLK_RATIO"] = 8 >> self.rtio.fine_ts_width self.config["DDS_CHANNEL_COUNT"] = 8 self.config["DDS_AD9858"] = True phy = dds.AD9858(platform.request("dds"), 8) @@ -210,6 +208,8 @@ class NIST_QC1(_NIST_QCx): rtio_channels.append(rtio.LogChannel()) self.add_rtio(rtio_channels) + assert self.rtio.fine_ts_width <= 3 + self.config["DDS_RTIO_CLK_RATIO"] = 8 >> self.rtio.fine_ts_width class NIST_QC2(_NIST_QCx): @@ -246,8 +246,6 @@ class NIST_QC2(_NIST_QCx): rtio_channels.append(rtio.Channel.from_phy(phy)) self.config["RTIO_DDS_CHANNEL"] = len(rtio_channels) - assert self.rtio.fine_ts_width <= 3 - self.config["DDS_RTIO_CLK_RATIO"] = 24 >> self.rtio.fine_ts_width self.config["DDS_CHANNEL_COUNT"] = 11 self.config["DDS_AD9914"] = True self.config["DDS_ONEHOT_SEL"] = True @@ -261,6 +259,8 @@ class NIST_QC2(_NIST_QCx): rtio_channels.append(rtio.LogChannel()) self.add_rtio(rtio_channels) + assert self.rtio.fine_ts_width <= 3 + self.config["DDS_RTIO_CLK_RATIO"] = 24 >> self.rtio.fine_ts_width def main():