From cb247f235f552053323ec62d8256c84d3cd49bb9 Mon Sep 17 00:00:00 2001 From: occheung Date: Mon, 8 Nov 2021 12:42:05 +0800 Subject: [PATCH] gateware: pass adr_w/data_w to submodules --- artiq/gateware/amp/kernel_cpu.py | 10 ++++++---- artiq/gateware/amp/soc.py | 16 ++++++++++------ artiq/gateware/targets/kasli.py | 12 ++++++------ artiq/gateware/targets/kc705.py | 10 +++++----- artiq/gateware/targets/metlino.py | 4 ++-- artiq/gateware/targets/sayma_amc.py | 2 +- artiq/gateware/targets/sayma_rtm.py | 2 +- 7 files changed, 31 insertions(+), 25 deletions(-) diff --git a/artiq/gateware/amp/kernel_cpu.py b/artiq/gateware/amp/kernel_cpu.py index bea786be9..6979b7b4f 100644 --- a/artiq/gateware/amp/kernel_cpu.py +++ b/artiq/gateware/amp/kernel_cpu.py @@ -1,4 +1,5 @@ from migen import * +from migen.build.platforms.sinara import kasli from misoc.interconnect.csr import * from misoc.interconnect import wishbone from misoc.cores import vexriscv @@ -14,8 +15,6 @@ class KernelCPU(Module): # # # - self._wb_slaves = WishboneSlaveManager(0x80000000) - # CPU core self.clock_domains.cd_sys_kernel = ClockDomain() self.comb += [ @@ -26,9 +25,12 @@ class KernelCPU(Module): self.submodules.cpu = ClockDomainsRenamer("sys_kernel")( vexriscv.VexRiscv(platform, exec_address, variant="VexRiscv_IMA" if kasli_v1 else "VexRiscv_G")) + + self.cpu_dw = len(self.cpu.dbus.dat_w) + self._wb_slaves = WishboneSlaveManager(0x80000000, dw=self.cpu_dw) # DRAM access - self.wb_sdram = wishbone.Interface() + self.wb_sdram = wishbone.Interface(data_width=self.cpu_dw, adr_width=32-log2_int(self.cpu_dw//8)) self.add_wb_slave(main_mem_origin, 0x10000000, self.wb_sdram) def get_csrs(self): @@ -37,7 +39,7 @@ class KernelCPU(Module): def do_finalize(self): self.submodules.wishbonecon = wishbone.InterconnectShared( [self.cpu.ibus, self.cpu.dbus], - self._wb_slaves.get_interconnect_slaves(), register=True) + self._wb_slaves.get_interconnect_slaves(), register=True, dw=self.cpu_dw) def add_wb_slave(self, origin, length, interface): if self.finalized: diff --git a/artiq/gateware/amp/soc.py b/artiq/gateware/amp/soc.py index 76d79807c..91b75ca3a 100644 --- a/artiq/gateware/amp/soc.py +++ b/artiq/gateware/amp/soc.py @@ -1,3 +1,4 @@ +from migen import * from misoc.cores import timer from misoc.interconnect import wishbone @@ -19,21 +20,24 @@ class AMPSoC: self.csr_devices.append("kernel_cpu") mailbox_size = 3 - self.submodules.mailbox = Mailbox(mailbox_size) - self.add_wb_slave(self.mem_map["mailbox"], 4*mailbox_size, + self.csr_separation = self.kernel_cpu.cpu_dw//8 + + self.submodules.mailbox = Mailbox(mailbox_size, adr_width=32-log2_int(self.csr_separation)) + self.add_wb_slave(self.mem_map["mailbox"], self.csr_separation*mailbox_size, self.mailbox.i1) - self.kernel_cpu.add_wb_slave(self.mem_map["mailbox"], 4*mailbox_size, + self.kernel_cpu.add_wb_slave(self.mem_map["mailbox"], self.csr_separation*mailbox_size, self.mailbox.i2) self.add_memory_region("mailbox", self.mem_map["mailbox"] | 0x80000000, - 4*mailbox_size) + self.csr_separation*mailbox_size) def register_kernel_cpu_csrdevice(self, name, csrs=None): if csrs is None: csrs = getattr(self, name).get_csrs() - bank = wishbone.CSRBank(csrs) + csr_bus = wishbone.Interface(data_width=32, adr_width=32-log2_int(self.csr_separation)) + bank = wishbone.CSRBank(csrs, bus=csr_bus) self.submodules += bank - self.kernel_cpu.add_wb_slave(self.mem_map[name], 4*2**bank.decode_bits, bank.bus) + self.kernel_cpu.add_wb_slave(self.mem_map[name], self.csr_separation*2**bank.decode_bits, bank.bus) self.add_csr_region(name, self.mem_map[name] | 0x80000000, 32, csrs) diff --git a/artiq/gateware/targets/kasli.py b/artiq/gateware/targets/kasli.py index 5cba517a7..311028fcb 100755 --- a/artiq/gateware/targets/kasli.py +++ b/artiq/gateware/targets/kasli.py @@ -144,7 +144,7 @@ class StandaloneBase(MiniSoC, AMPSoC): self.csr_devices.append("rtio_core") self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc) self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")( - rtio.DMA(self.get_native_sdram_if())) + rtio.DMA(self.get_native_sdram_if(), self.cpu_dw)) self.register_kernel_cpu_csrdevice("rtio") self.register_kernel_cpu_csrdevice("rtio_dma") self.submodules.cri_con = rtio.CRIInterconnectShared( @@ -162,7 +162,7 @@ class StandaloneBase(MiniSoC, AMPSoC): self.rtio_crg.cd_rtio.clk) self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio_tsc, self.rtio_core.cri, - self.get_native_sdram_if()) + self.get_native_sdram_if(), cpu_dw=self.cpu_dw) self.csr_devices.append("rtio_analyzer") @@ -345,7 +345,7 @@ class MasterBase(MiniSoC, AMPSoC): self.drtio_cri.append(core.cri) self.csr_devices.append(core_name) - coreaux = cdr(DRTIOAuxController(core.link_layer)) + coreaux = cdr(DRTIOAuxController(core.link_layer, self.cpu_dw)) setattr(self.submodules, coreaux_name, coreaux) self.csr_devices.append(coreaux_name) @@ -386,7 +386,7 @@ class MasterBase(MiniSoC, AMPSoC): self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc) self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")( - rtio.DMA(self.get_native_sdram_if())) + rtio.DMA(self.get_native_sdram_if(), self.cpu_dw)) self.register_kernel_cpu_csrdevice("rtio") self.register_kernel_cpu_csrdevice("rtio_dma") self.submodules.cri_con = rtio.CRIInterconnectShared( @@ -398,7 +398,7 @@ class MasterBase(MiniSoC, AMPSoC): self.csr_devices.append("routing_table") self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio_tsc, self.cri_con.switch.slave, - self.get_native_sdram_if()) + self.get_native_sdram_if(), cpu_dw=self.cpu_dw) self.csr_devices.append("rtio_analyzer") # Never running out of stupid features, GTs on A7 make you pack @@ -539,7 +539,7 @@ class SatelliteBase(BaseSoC): self.drtio_cri.append(core.cri) self.csr_devices.append(corerep_name) - coreaux = cdr(DRTIOAuxController(core.link_layer)) + coreaux = cdr(DRTIOAuxController(core.link_layer, self.cpu_dw)) setattr(self.submodules, coreaux_name, coreaux) self.csr_devices.append(coreaux_name) diff --git a/artiq/gateware/targets/kc705.py b/artiq/gateware/targets/kc705.py index 6e1fdd1d4..4cec96e87 100755 --- a/artiq/gateware/targets/kc705.py +++ b/artiq/gateware/targets/kc705.py @@ -177,7 +177,7 @@ class _StandaloneBase(MiniSoC, AMPSoC): self.csr_devices.append("rtio_core") self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc) self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")( - rtio.DMA(self.get_native_sdram_if())) + rtio.DMA(self.get_native_sdram_if(), self.cpu_dw)) self.register_kernel_cpu_csrdevice("rtio") self.register_kernel_cpu_csrdevice("rtio_dma") self.submodules.cri_con = rtio.CRIInterconnectShared( @@ -193,7 +193,7 @@ class _StandaloneBase(MiniSoC, AMPSoC): self.rtio_crg.cd_rtio.clk) self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio_tsc, self.rtio_core.cri, - self.get_native_sdram_if()) + self.get_native_sdram_if(), cpu_dw=self.cpu_dw) self.csr_devices.append("rtio_analyzer") @@ -265,7 +265,7 @@ class _MasterBase(MiniSoC, AMPSoC): self.drtio_cri.append(core.cri) self.csr_devices.append(core_name) - coreaux = cdr(DRTIOAuxController(core.link_layer)) + coreaux = cdr(DRTIOAuxController(core.link_layer, self.cpu_dw)) setattr(self.submodules, coreaux_name, coreaux) self.csr_devices.append(coreaux_name) @@ -323,7 +323,7 @@ class _MasterBase(MiniSoC, AMPSoC): self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc) self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")( - rtio.DMA(self.get_native_sdram_if())) + rtio.DMA(self.get_native_sdram_if(), self.cpu_dw)) self.register_kernel_cpu_csrdevice("rtio") self.register_kernel_cpu_csrdevice("rtio_dma") self.submodules.cri_con = rtio.CRIInterconnectShared( @@ -407,7 +407,7 @@ class _SatelliteBase(BaseSoC): self.drtio_cri.append(core.cri) self.csr_devices.append(corerep_name) - coreaux = cdr(DRTIOAuxController(core.link_layer)) + coreaux = cdr(DRTIOAuxController(core.link_layer, self.cpu_dw)) setattr(self.submodules, coreaux_name, coreaux) self.csr_devices.append(coreaux_name) diff --git a/artiq/gateware/targets/metlino.py b/artiq/gateware/targets/metlino.py index 107dbc78d..ffb2b38b9 100755 --- a/artiq/gateware/targets/metlino.py +++ b/artiq/gateware/targets/metlino.py @@ -97,7 +97,7 @@ class Master(MiniSoC, AMPSoC): drtio_cri.append(core.cri) self.csr_devices.append(core_name) - coreaux = cdr(DRTIOAuxController(core.link_layer)) + coreaux = cdr(DRTIOAuxController(core.link_layer, self.cpu_dw)) setattr(self.submodules, coreaux_name, coreaux) self.csr_devices.append(coreaux_name) @@ -150,7 +150,7 @@ class Master(MiniSoC, AMPSoC): self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc) self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")( - rtio.DMA(self.get_native_sdram_if())) + rtio.DMA(self.get_native_sdram_if(), self.cpu_dw)) self.register_kernel_cpu_csrdevice("rtio") self.register_kernel_cpu_csrdevice("rtio_dma") self.submodules.cri_con = rtio.CRIInterconnectShared( diff --git a/artiq/gateware/targets/sayma_amc.py b/artiq/gateware/targets/sayma_amc.py index 32ebc8521..527d37b5c 100755 --- a/artiq/gateware/targets/sayma_amc.py +++ b/artiq/gateware/targets/sayma_amc.py @@ -118,7 +118,7 @@ class SatelliteBase(MiniSoC): self.drtio_cri.append(core.cri) self.csr_devices.append(corerep_name) - coreaux = cdr(DRTIOAuxController(core.link_layer)) + coreaux = cdr(DRTIOAuxController(core.link_layer, self.cpu_dw)) setattr(self.submodules, coreaux_name, coreaux) self.csr_devices.append(coreaux_name) diff --git a/artiq/gateware/targets/sayma_rtm.py b/artiq/gateware/targets/sayma_rtm.py index a132601d6..9d8a818b4 100755 --- a/artiq/gateware/targets/sayma_rtm.py +++ b/artiq/gateware/targets/sayma_rtm.py @@ -80,7 +80,7 @@ class _SatelliteBase(BaseSoC): self.submodules.drtiosat = core self.csr_devices.append("drtiosat") - coreaux = cdr(DRTIOAuxController(core.link_layer)) + coreaux = cdr(DRTIOAuxController(core.link_layer, self.cpu_dw)) self.submodules.drtioaux0 = coreaux self.csr_devices.append("drtioaux0")