srenblad/artiq
1
0
Fork 0
forked from M-Labs/artiq
Code Pull Requests Activity

coredevice/shiftreg: add get method

Browse Source
This commit is contained in:
Sebastien Bourdeauducq 2019-12-20 18:58:50 +08:00
parent b7f1623197
commit cab8c8249e
1 changed files with 18 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

19
artiq/coredevice/shiftreg.py
View File

@ -6,13 +6,15 @@ class ShiftReg:
"""Driver for shift registers/latch combos connected to TTLs""" """Driver for shift registers/latch combos connected to TTLs"""
kernel_invariants = {"dt", "n"} kernel_invariants = {"dt", "n"}
def __init__(self, dmgr, clk, ser, latch, n=32, dt=10*us): def __init__(self, dmgr, clk, ser, latch, n=32, dt=10*us, ser_in=None):
self.core = dmgr.get("core") self.core = dmgr.get("core")
self.clk = dmgr.get(clk) self.clk = dmgr.get(clk)
self.ser = dmgr.get(ser) self.ser = dmgr.get(ser)
self.latch = dmgr.get(latch) self.latch = dmgr.get(latch)
self.n = n self.n = n
self.dt = dt self.dt = dt
if ser_in is not None:
self.ser_in = dmgr.get(ser_in)
@kernel @kernel
def set(self, data): def set(self, data):
@ -34,3 +36,18 @@ class ShiftReg:
delay(self.dt) delay(self.dt)
self.latch.off() self.latch.off()
delay(self.dt) delay(self.dt)
@kernel
def get(self):
delay(-2*(self.n + 1)*self.dt)
data = 0
for i in range(self.n):
data <<= 1
if self.ser_in.sample_input():
data |= 1
delay(self.dt)
self.clk.on()
delay(self.dt)
self.clk.off()
delay(self.dt)
return data