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phaser: cleanup jesd phy instantiation a bit

This commit is contained in:
Robert Jördens 2016-10-13 14:43:24 +02:00
parent 01bfe54dde
commit c8e45ae3f6
1 changed files with 2 additions and 3 deletions
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5
artiq/gateware/targets/kc705.py
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@ -472,15 +472,14 @@ class AD9154(Module, AutoCSR):
jesd_phy = JESD204BPhyTX( jesd_phy = JESD204BPhyTX(
jesd_qpll, platform.request("ad9154_jesd", i), jesd_qpll, platform.request("ad9154_jesd", i),
rtio_freq) rtio_freq)
jesd_phys.append(jesd_phy)
setattr(self.submodules, "jesd_phy"+str(i), jesd_phy)
for jesd_phy in jesd_phys:
platform.add_period_constraint( platform.add_period_constraint(
jesd_phy.gtx.cd_tx.clk, jesd_phy.gtx.cd_tx.clk,
40/jesd_linerate*1e9) 40/jesd_linerate*1e9)
platform.add_false_path_constraints( platform.add_false_path_constraints(
rtio_crg.cd_rtio.clk, rtio_crg.cd_rtio.clk,
jesd_phy.gtx.cd_tx.clk) jesd_phy.gtx.cd_tx.clk)
jesd_phys.append(jesd_phy)
setattr(self.submodules, "jesd_phy"+str(i), jesd_phy)
self.submodules.jesd_core = JESD204BCoreTX( self.submodules.jesd_core = JESD204BCoreTX(
jesd_phys, jesd_settings, converter_data_width=32) jesd_phys, jesd_settings, converter_data_width=32)
self.comb += self.jesd_core.start.eq(jesd_sync) self.comb += self.jesd_core.start.eq(jesd_sync)