srenblad
/
artiq
forked from M-Labs/artiq
1
0
Fork 0
Code Pull Requests Activity

fastino: add comments about sideeffects on v0.1

This commit is contained in:
Robert Jördens 2022-02-16 14:42:22 +00:00
parent 08b65470cd
commit c8b9eed9c9
1 changed files with 9 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
artiq/coredevice/fastino.py
View File

@ -65,6 +65,9 @@ class Fastino:
It does not change set channel voltages and does not reset the PLLs or clock It does not change set channel voltages and does not reset the PLLs or clock
domains. domains.
Note: On Fastino gateware before v0.2 this may lead to 0 voltage being emitted
transiently.
""" """
self.set_cfg(reset=0, afe_power_down=0, dac_clr=0, clr_err=1) self.set_cfg(reset=0, afe_power_down=0, dac_clr=0, clr_err=1)
delay_mu(self.t_frame) delay_mu(self.t_frame)
@ -274,9 +277,12 @@ class Fastino:
def apply_cic(self, channel_mask): def apply_cic(self, channel_mask):
"""Apply the staged interpolator configuration on the specified channels. """Apply the staged interpolator configuration on the specified channels.
Each Fastino channel includes a fourth order (cubic) CIC interpolator with Each Fastino channel starting with gateware v0.2 includes a fourth order
variable rate change and variable output gain compensation (see (cubic) CIC interpolator with variable rate change and variable output
:meth:`stage_cic`). gain compensation (see :meth:`stage_cic`).
Fastino gateware before v0.2 does not include the interpolators and the
methods affecting the CICs should not be used.
Channels using non-unity interpolation rate should have Channels using non-unity interpolation rate should have
continous DAC updates enabled (see :meth:`set_continuous`) unless continous DAC updates enabled (see :meth:`set_continuous`) unless