srenblad
/
artiq
forked from M-Labs/artiq
1
0
Fork 0
Code Pull Requests Activity

gateware: add fastino inject WIP

This commit is contained in:
Simon Renblad 2024-07-17 17:34:40 +08:00
parent 9f019a3f28
commit c87e43f3e5
1 changed files with 18 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

19
artiq/gateware/rtio/phy/fastino.py
View File

@ -28,6 +28,10 @@ class Fastino(Module):
# dac data words # dac data words
dacs = [Signal(16) for i in range(32)] dacs = [Signal(16) for i in range(32)]
self.probes = dacs self.probes = dacs
staged_dacs = [Signal(16) for i in range(32)]
override_en = [Signal() for i in range(32)]
override_o = [Signal(16) for i in range(32)]
self.overrides = override_en + override_o
header = Record([ header = Record([
("cfg", 4), ("cfg", 4),
@ -93,13 +97,21 @@ class Fastino(Module):
header.typ.eq(1), header.typ.eq(1),
], ],
} }
overrides = {
"default": []
}
for i in range(0, len(dacs), width): for i in range(0, len(dacs), width):
cases[i] = [ cases[i] = [
Cat(dacs[i:i + width]).eq(self.rtlink.o.data), Cat(staged_dacs[i:i + width]).eq(self.rtlink.o.data),
[If(~hold[i + j] & (header.typ == 0), [If(~hold[i + j] & (header.typ == 0),
header.enable[i + j].eq(1), header.enable[i + j].eq(1),
) for j in range(width)] ) for j in range(width)]
] ]
overrides[i] = If(override_en[i],
Cat(staged_dacs[i:i + width]).eq(Replicate(override_o[i], width))
).Else(
Cat(staged_dacs[i:i + width]).eq(self.rtlink.o.data)
)
self.comb += [ self.comb += [
If(header.typ == 0, If(header.typ == 0,
@ -119,6 +131,11 @@ class Fastino(Module):
If(self.rtlink.o.stb, If(self.rtlink.o.stb,
Case(self.rtlink.o.address, cases), Case(self.rtlink.o.address, cases),
), ),
[If(override_en[i],
Cat(dacs[i:i + width]).eq(Cat(override_o[i:i + width]))
).Else(
Cat(dacs[i:i + width]).eq(Cat(staged_dacs[i: i + width]))
) for i in range(0, len(dacs), width)]
] ]
self.sync += [ self.sync += [