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sayma_amc: work around Ultrascale LVDS Toutbuf_delay_td_pad

This commit is contained in:
Sebastien Bourdeauducq 2019-01-09 13:47:08 +08:00
parent 62599c5f91
commit c7b18952b8
1 changed files with 12 additions and 0 deletions
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12
artiq/gateware/targets/sayma_amc.py
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@ -400,6 +400,17 @@ class MasterDAC(MiniSoC, AMPSoC, RTMCommon):
self.csr_devices.append("sysref_sampler") self.csr_devices.append("sysref_sampler")
def workaround_us_lvds_tristate(platform):
# Those shoddy Kintex Ultrascale FPGAs take almost a microsecond to change the direction of a
# LVDS I/O buffer. The application has to cope with it and this cannot be handled at static
# timing analysis. Disable the latter for IOBUFDS.
# See:
# https://forums.xilinx.com/t5/Timing-Analysis/Delay-890-ns-in-OBUFTDS-in-Kintex-UltraScale/td-p/868364
# FIXME: this is a bit zealous. Xilinx SR in progress to find a more selective command.
platform.add_platform_command(
"set_false_path -through [get_pins -filter {{REF_PIN_NAME == O}} -of [get_cells -filter {{REF_NAME == IOBUFDS}}]]")
class Master(MiniSoC, AMPSoC): class Master(MiniSoC, AMPSoC):
""" """
DRTIO master with 2 SFP ports plus 8 lanes on RTM. DRTIO master with 2 SFP ports plus 8 lanes on RTM.
@ -528,6 +539,7 @@ class Master(MiniSoC, AMPSoC):
iostandard="LVDS") iostandard="LVDS")
eem.Zotino.add_std(self, 3, ttl_simple.Output, eem.Zotino.add_std(self, 3, ttl_simple.Output,
iostandard="LVDS") iostandard="LVDS")
workaround_us_lvds_tristate(platform)
self.config["HAS_RTIO_LOG"] = None self.config["HAS_RTIO_LOG"] = None
self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels) self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)