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sayma: add many-port pure DRTIO master

This commit is contained in:
Sebastien Bourdeauducq 2018-06-25 18:21:22 +08:00
parent 84b3d9ecc6
commit c750de2955
2 changed files with 150 additions and 13 deletions

View File

@ -115,6 +115,9 @@ class RTMCommon:
class Standalone(MiniSoC, AMPSoC, RTMCommon): class Standalone(MiniSoC, AMPSoC, RTMCommon):
"""
Local DAC/SAWG channels only.
"""
mem_map = { mem_map = {
"cri_con": 0x10000000, "cri_con": 0x10000000,
"rtio": 0x11000000, "rtio": 0x11000000,
@ -216,7 +219,10 @@ class Standalone(MiniSoC, AMPSoC, RTMCommon):
self.csr_devices.append("sysref_sampler") self.csr_devices.append("sysref_sampler")
class Master(MiniSoC, AMPSoC, RTMCommon): class MasterDAC(MiniSoC, AMPSoC, RTMCommon):
"""
DRTIO master with local DAC/SAWG channels.
"""
mem_map = { mem_map = {
"cri_con": 0x10000000, "cri_con": 0x10000000,
"rtio": 0x11000000, "rtio": 0x11000000,
@ -358,7 +364,135 @@ class Master(MiniSoC, AMPSoC, RTMCommon):
self.csr_devices.append("sysref_sampler") self.csr_devices.append("sysref_sampler")
class Master(MiniSoC, AMPSoC):
"""
DRTIO master with 2 SFP ports plus 8 lanes on RTM.
Use passive RTM adapter to connect to satellites.
Due to GTH clock routing restrictions, it is not possible
to use more RTM lanes without additional hardware.
"""
mem_map = {
"cri_con": 0x10000000,
"rtio": 0x11000000,
"rtio_dma": 0x12000000,
"drtio_aux": 0x14000000,
"mailbox": 0x70000000
}
mem_map.update(MiniSoC.mem_map)
def __init__(self, with_sawg, **kwargs):
MiniSoC.__init__(self,
cpu_type="or1k",
sdram_controller_type="minicon",
l2_size=128*1024,
ident=artiq_version,
ethmac_nrxslots=4,
ethmac_ntxslots=4,
**kwargs)
AMPSoC.__init__(self)
platform = self.platform
rtio_clk_freq = 150e6
self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n)
self.csr_devices.append("si5324_rst_n")
i2c = self.platform.request("i2c")
self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
self.csr_devices.append("i2c")
self.config["I2C_BUS_COUNT"] = 1
self.config["HAS_SI5324"] = None
self.config["SI5324_AS_SYNTHESIZER"] = None
self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
self.comb += [
platform.request("sfp_tx_disable", i).eq(0)
for i in range(2)
]
self.submodules.drtio_transceiver = gth_ultrascale.GTH(
clock_pads=platform.request("si5324_clkout", 0),
data_pads=[platform.request("sfp", i) for i in range(2)] +
[platform.request("rtm_gth", i) for i in range(8)],
sys_clk_freq=self.clk_freq,
rtio_clk_freq=rtio_clk_freq)
self.csr_devices.append("drtio_transceiver")
drtio_csr_group = []
drtio_memory_group = []
drtio_cri = []
for i in range(10):
core_name = "drtio" + str(i)
memory_name = "drtio" + str(i) + "_aux"
drtio_csr_group.append(core_name)
drtio_memory_group.append(memory_name)
core = ClockDomainsRenamer({"rtio_rx": "rtio_rx"+str(i)})(
DRTIOMaster(self.drtio_transceiver.channels[i]))
setattr(self.submodules, core_name, core)
drtio_cri.append(core.cri)
self.csr_devices.append(core_name)
memory_address = self.mem_map["drtio_aux"] + 0x800*i
self.add_wb_slave(memory_address, 0x800,
core.aux_controller.bus)
self.add_memory_region(memory_name, memory_address | self.shadow_base, 0x800)
self.config["HAS_DRTIO"] = None
self.add_csr_group("drtio", drtio_csr_group)
self.add_memory_group("drtio_aux", drtio_memory_group)
rtio_clk_period = 1e9/rtio_clk_freq
gth = self.drtio_transceiver.gths[0]
platform.add_period_constraint(gth.txoutclk, rtio_clk_period)
platform.add_period_constraint(gth.rxoutclk, rtio_clk_period)
platform.add_false_path_constraints(
self.crg.cd_sys.clk,
gth.txoutclk, gth.rxoutclk)
for gth in self.drtio_transceiver.gths[1:]:
platform.add_period_constraint(gth.rxoutclk, rtio_clk_period)
platform.add_false_path_constraints(
self.crg.cd_sys.clk, gth.rxoutclk)
rtio_channels = []
for i in range(4):
phy = ttl_simple.Output(platform.request("user_led", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
sma_io = platform.request("sma_io", 0)
self.comb += sma_io.direction.eq(1)
phy = ttl_simple.Output(sma_io.level)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
sma_io = platform.request("sma_io", 1)
self.comb += sma_io.direction.eq(0)
phy = ttl_simple.InOut(sma_io.level)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
self.config["HAS_RTIO_LOG"] = None
self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
rtio_channels.append(rtio.LogChannel())
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
self.csr_devices.append("rtio_moninj")
self.submodules.rtio_core = rtio.Core(rtio_channels, glbl_fine_ts_width=3)
self.csr_devices.append("rtio_core")
self.submodules.rtio = rtio.KernelInitiator()
self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")(
rtio.DMA(self.get_native_sdram_if()))
self.register_kernel_cpu_csrdevice("rtio")
self.register_kernel_cpu_csrdevice("rtio_dma")
self.submodules.cri_con = rtio.CRIInterconnectShared(
[self.rtio.cri, self.rtio_dma.cri],
[self.rtio_core.cri] + drtio_cri)
self.register_kernel_cpu_csrdevice("cri_con")
class Satellite(BaseSoC, RTMCommon): class Satellite(BaseSoC, RTMCommon):
"""
DRTIO satellite with local DAC/SAWG channels.
Use SFP0 to connect to master (Kasli/Sayma).
"""
mem_map = { mem_map = {
"serwb": 0x13000000, "serwb": 0x13000000,
"drtio_aux": 0x14000000, "drtio_aux": 0x14000000,
@ -474,7 +608,7 @@ def main():
parser.set_defaults(output_dir="artiq_sayma") parser.set_defaults(output_dir="artiq_sayma")
parser.add_argument("-V", "--variant", default="standalone", parser.add_argument("-V", "--variant", default="standalone",
help="variant: " help="variant: "
"standalone/master/satellite " "standalone/masterdac/master/satellite "
"(default: %(default)s)") "(default: %(default)s)")
parser.add_argument("--rtm-csr-csv", parser.add_argument("--rtm-csr-csv",
default=os.path.join("artiq_sayma", "rtm_gateware", "rtm_csr.csv"), default=os.path.join("artiq_sayma", "rtm_gateware", "rtm_csr.csv"),
@ -488,6 +622,8 @@ def main():
variant = args.variant.lower() variant = args.variant.lower()
if variant == "standalone": if variant == "standalone":
cls = Standalone cls = Standalone
elif variant == "masterdac":
cls = MasterDAC
elif variant == "master": elif variant == "master":
cls = Master cls = Master
elif variant == "satellite": elif variant == "satellite":
@ -496,16 +632,17 @@ def main():
raise SystemExit("Invalid variant (-V/--variant)") raise SystemExit("Invalid variant (-V/--variant)")
soc = cls(with_sawg=not args.without_sawg, **soc_sdram_argdict(args)) soc = cls(with_sawg=not args.without_sawg, **soc_sdram_argdict(args))
remote_csr_regions = remote_csr.get_remote_csr_regions( if variant != "master":
soc.mem_map["serwb"] | soc.shadow_base, remote_csr_regions = remote_csr.get_remote_csr_regions(
args.rtm_csr_csv) soc.mem_map["serwb"] | soc.shadow_base,
for name, origin, busword, csrs in remote_csr_regions: args.rtm_csr_csv)
soc.add_csr_region(name, origin, busword, csrs) for name, origin, busword, csrs in remote_csr_regions:
# Configuration for RTM peripherals. Keep in sync with sayma_rtm.py! soc.add_csr_region(name, origin, busword, csrs)
soc.config["HAS_HMC830_7043"] = None # Configuration for RTM peripherals. Keep in sync with sayma_rtm.py!
soc.config["CONVERTER_SPI_HMC830_CS"] = 0 soc.config["HAS_HMC830_7043"] = None
soc.config["CONVERTER_SPI_HMC7043_CS"] = 1 soc.config["CONVERTER_SPI_HMC830_CS"] = 0
soc.config["CONVERTER_SPI_FIRST_AD9154_CS"] = 2 soc.config["CONVERTER_SPI_HMC7043_CS"] = 1
soc.config["CONVERTER_SPI_FIRST_AD9154_CS"] = 2
build_artiq_soc(soc, builder_argdict(args)) build_artiq_soc(soc, builder_argdict(args))

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@ -14,7 +14,7 @@ requirements:
run: run:
- python >=3.5.3,<3.6 - python >=3.5.3,<3.6
- setuptools 33.1.1 - setuptools 33.1.1
- migen 0.7 py35_51+git9929b23 - migen 0.7 py35_66+gitdcfec40
- misoc 0.11 py35_20+git2436a68d - misoc 0.11 py35_20+git2436a68d
- jesd204b 0.7 - jesd204b 0.7
- microscope - microscope