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moninj: do not require a rsys clock domain

This commit is contained in:
Sebastien Bourdeauducq 2017-02-20 15:52:48 +08:00
parent 8da28177a4
commit c66efc0279
1 changed files with 1 additions and 1 deletions
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artiq/gateware/rtio/moninj.py
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@ -20,7 +20,7 @@ class Monitor(Module, AutoCSR):
for cp in chan_probes: for cp in chan_probes:
cp_sys = [] cp_sys = []
for p in cp: for p in cp:
vs = BusSynchronizer(len(p), "rio", "rsys") vs = BusSynchronizer(len(p), "rio", "sys")
self.submodules += vs self.submodules += vs
self.comb += vs.i.eq(p) self.comb += vs.i.eq(p)
cp_sys.append(vs.o) cp_sys.append(vs.o)