forked from M-Labs/artiq
drtio: clock domains
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@ -1,16 +1,31 @@
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from types import SimpleNamespace
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from migen import *
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from artiq.gateware.drtio import link_layer, rt_packets, iot
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class DRTIOSatellite(Module):
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def __init__(self, transceiver, channels, fine_ts_width=3, full_ts_width=63):
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def __init__(self, transceiver, rx_synchronizer, channels, fine_ts_width=3, full_ts_width=63):
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self.submodules.link_layer = link_layer.LinkLayer(
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transceiver.encoder, transceiver.decoders)
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self.submodules.rt_packets = rt_packets.RTPacketSatellite(
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self.link_layer)
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self.submodules.iot = iot.IOT(
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self.rt_packets, channels, fine_ts_width, full_ts_width)
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link_layer_sync = SimpleNamespace(
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tx_aux_frame=self.link_layer.tx.aux_frame,
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tx_aux_data=self.link_layer.tx_aux_data,
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tx_aux_ack=self.link_layer.tx_aux_ack,
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tx_rt_frame=self.link_layer.tx_rt_frame,
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tx_rt_data=self.link_layer.tx_rt_data,
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rx_aux_stb=rx_synchronizer.sync(self.link_layer.rx_aux_stb),
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rx_aux_frame=rx_synchronizer.sync(self.link_layer.rx_aux_frame),
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rx_aux_data=rx_synchronizer.sync(self.link_layer.rx_aux_data),
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rx_rt_frame=rx_synchronizer.sync(self.link_layer.rx_rt_frame),
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rx_rt_data=rx_synchronizer.sync(self.link_layer.rx_rt_data)
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)
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self.submodules.rt_packets = ClockDomainsRenamer("rtio")(
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rt_packets.RTPacketSatellite(link_layer_sync))
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self.submodules.iot = ClockDomainsRenamer("rtio")(
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iot.IOT(self.rt_packets, channels, fine_ts_width, full_ts_width))
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class DRTIOMaster(Module):
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@ -3,6 +3,7 @@ from operator import xor, or_
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from migen import *
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from migen.genlib.fsm import *
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from migen.genlib.cdc import MultiReg
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class Scrambler(Module):
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@ -210,24 +211,26 @@ class LinkLayerRX(Module):
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class LinkLayer(Module):
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def __init__(self, encoder, decoders):
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# control signals, in rtio clock domain
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self.reset = Signal()
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self.ready = Signal()
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# pulsed to reset receiver, rx_ready must immediately go low
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self.rx_reset = Signal()
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# receiver locked including comma alignment
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self.rx_ready = Signal()
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tx = LinkLayerTX(encoder)
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rx = LinkLayerRX(decoders)
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tx = ClockDomainsRenamer("rtio")(LinkLayerTX(encoder))
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rx = ClockDomainsRenamer("rtio_rx")(LinkLayerRX(decoders))
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self.submodules += tx, rx
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# in rtio clock domain
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self.tx_aux_frame = tx.aux_frame
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self.tx_aux_data = tx.aux_data
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self.tx_aux_ack = tx.aux_ack
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self.tx_rt_frame = tx.rt_frame
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self.tx_rt_data = tx.rt_data
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# in rtio_rx clock domain
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self.rx_aux_stb = rx.aux_stb
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self.rx_aux_frame = rx.aux_frame
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self.rx_aux_data = rx.aux_data
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@ -236,11 +239,19 @@ class LinkLayer(Module):
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# # #
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fsm = ResetInserter()(FSM(reset_state="RESET_RX"))
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fsm = ClockDomainsRenamer("rtio")(
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ResetInserter()(FSM(reset_state="RESET_RX")))
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self.submodules += fsm
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self.comb += fsm.reset.eq(self.reset)
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rx_remote_rx_ready = Signal()
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rx_link_init = Signal()
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self.specials += [
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MultiReg(rx.remote_rx_ready, rx_remote_rx_ready, "rtio"),
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MultiReg(rx.link_init, rx_link_init, "rtio")
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]
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fsm.act("RESET_RX",
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tx.link_init.eq(1),
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self.rx_reset.eq(1),
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@ -255,14 +266,14 @@ class LinkLayer(Module):
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fsm.act("WAIT_REMOTE_RX_READY",
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tx.link_init.eq(1),
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tx.signal_rx_ready.eq(1),
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If(rx.remote_rx_ready,
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If(rx_remote_rx_ready,
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NextState("WAIT_REMOTE_LINK_UP")
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)
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)
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fsm.act("WAIT_REMOTE_LINK_UP",
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If(~rx.link_init, NextState("READY"))
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If(~rx_link_init, NextState("READY"))
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)
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fsm.act("READY",
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If(rx.link_init, NextState("RESET_RX")),
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If(rx_link_init, NextState("RESET_RX")),
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self.ready.eq(1)
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)
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