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phaser: spi, sma_gpio: 2.5 V

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This commit is contained in:
Robert Jördens 2016-10-27 15:39:39 +02:00
parent 65b2e4464c
commit c428800caf
2 changed files with 4 additions and 4 deletions
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6
artiq/gateware/phaser.py
View File

@ -13,10 +13,10 @@ fmc_adapter_io = [
Subsignal("mosi", Pins("HPC:LA03_N")), Subsignal("mosi", Pins("HPC:LA03_N")),
Subsignal("miso", Pins("HPC:LA04_P")), Subsignal("miso", Pins("HPC:LA04_P")),
Subsignal("en", Pins("HPC:LA05_N")), Subsignal("en", Pins("HPC:LA05_N")),
IOStandard("LVTTL"), IOStandard("LVCMOS25"),
), ),
("ad9154_txen", 0, Pins("HPC:LA07_P"), IOStandard("LVTTL")), ("ad9154_txen", 0, Pins("HPC:LA07_P"), IOStandard("LVCMOS25")),
("ad9154_txen", 1, Pins("HPC:LA07_N"), IOStandard("LVTTL")), ("ad9154_txen", 1, Pins("HPC:LA07_N"), IOStandard("LVCMOS25")),
("ad9154_refclk", 0, ("ad9154_refclk", 0,
Subsignal("p", Pins("HPC:GBTCLK0_M2C_P")), Subsignal("p", Pins("HPC:GBTCLK0_M2C_P")),
Subsignal("n", Pins("HPC:GBTCLK0_M2C_N")), Subsignal("n", Pins("HPC:GBTCLK0_M2C_N")),

2
artiq/gateware/targets/kc705.py
View File

@ -537,7 +537,7 @@ class Phaser(_NIST_Ions):
rtio_channels = [] rtio_channels = []
phy = ttl_serdes_7series.Inout_8X( phy = ttl_serdes_7series.Inout_8X(
platform.request("user_sma_gpio_n_33")) platform.request("user_sma_gpio_n"))
self.submodules += phy self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=128)) rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=128))