forked from M-Labs/artiq
drtio: handle underflow/sequence error CSRs
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@ -81,6 +81,14 @@ class RTController(Module):
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status_sequence_error = Signal()
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self.comb += self.kcsrs.o_status.status.eq(Cat(
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status_wait, status_underflow, status_sequence_error))
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sequence_error_set = Signal()
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underflow_set = Signal()
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self.sync += [
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If(self.kcsrs.o_underflow_reset.re, status_underflow.eq(0)),
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If(self.kcsrs.o_sequence_error_reset, status_sequence_error.eq(0)),
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If(underflow_set, status_underflow.eq(1)),
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If(sequence_error_set, status_sequence_error.eq(1)),
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]
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# TODO: collision, replace, busy
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cond_sequence_error = self.o_timestamp.storage < last_timestamps.dat_r
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