forked from M-Labs/artiq
suservo: drop adc idelays
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b44d6517d1
commit
c304b6207a
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@ -16,7 +16,6 @@ class SamplerPads(Module):
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dn = platform.request("{}_adc_data_n".format(eem0))
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clkout_se = Signal()
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clkout_d = Signal()
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sck = Signal()
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self.specials += [
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@ -25,13 +24,7 @@ class SamplerPads(Module):
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DDROutput(self.sck_en, 0, sck),
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DifferentialOutput(sck, spip.clk, spin.clk),
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DifferentialInput(dp.clkout, dn.clkout, clkout_se),
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Instance(
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"IDELAYE2",
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p_HIGH_PERFORMANCE_MODE="TRUE", p_IDELAY_TYPE="FIXED",
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p_SIGNAL_PATTERN="CLOCK", p_IDELAY_VALUE=0,
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p_REFCLK_FREQUENCY=200.,
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i_IDATAIN=clkout_se, o_DATAOUT=clkout_d),
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Instance("BUFR", i_I=clkout_d, o_O=self.clkout)
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Instance("BUFR", i_I=clkout_se, o_O=self.clkout)
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]
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# here to be early before the input delays below to have the clock
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@ -42,19 +35,12 @@ class SamplerPads(Module):
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clk=dp.clkout)
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# platform.add_period_constraint(sampler_pads.clkout_p, 8.)
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for i in "abcd":
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sdo_se = Signal()
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sdo = Signal()
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setattr(self, "sdo{}".format(i), sdo)
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sdop = getattr(dp, "sdo{}".format(i))
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sdon = getattr(dn, "sdo{}".format(i))
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self.specials += [
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DifferentialInput(sdop, sdon, sdo_se),
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Instance(
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"IDELAYE2",
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p_HIGH_PERFORMANCE_MODE="TRUE", p_IDELAY_TYPE="FIXED",
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p_SIGNAL_PATTERN="DATA", p_IDELAY_VALUE=15,
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p_REFCLK_FREQUENCY=200.,
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i_IDATAIN=sdo_se, o_DATAOUT=sdo),
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DifferentialInput(sdop, sdon, sdo),
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]
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# 8, -0+1.5 hold (t_HSDO_DDR), -0.5+0.5 skew
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platform.add_platform_command(
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