forked from M-Labs/artiq
shuttler: reorg SPI constants
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06426e0ed9
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c2d136f669
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@ -131,17 +131,30 @@ RELAY_SPI_CONFIG = (0*spi.SPI_OFFLINE | 1*spi.SPI_END |
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0*spi.SPI_CLK_POLARITY | 0*spi.SPI_CLK_PHASE |
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0*spi.SPI_LSB_FIRST | 0*spi.SPI_HALF_DUPLEX)
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SPI_CS_RELAY = 1 << 0
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SPI_CS_LED = 1 << 1
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SPI_DIV = 4
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ADC_SPI_CONFIG = (0*spi.SPI_OFFLINE | 0*spi.SPI_END |
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0*spi.SPI_INPUT | 0*spi.SPI_CS_POLARITY |
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1*spi.SPI_CLK_POLARITY | 1*spi.SPI_CLK_PHASE |
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0*spi.SPI_LSB_FIRST | 0*spi.SPI_HALF_DUPLEX)
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ADC_CS = 1
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ADC_SPI_DIV = 32
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# SPI clock write and read dividers
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# CS should assert at least 9.5 ns after clk pulse
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SPIT_RELAY_WR = 4
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# 25 ns high/low pulse hold (limiting for write)
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SPIT_ADC_WR = 4
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SPIT_ADC_RD = 16
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# SPI CS line
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CS_RELAY = 1 << 0
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CS_LED = 1 << 1
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CS_ADC = 1 << 0
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# Referenced AD4115 registers
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_AD4115_REG_STATUS = 0x00
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_AD4115_REG_ADCMODE = 0x01
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_AD4115_REG_DATA = 0x04
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_AD4115_REG_ID = 0x07
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_AD4115_REG_CH0 = 0x10
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_AD4115_REG_SETUPCON0 = 0x20
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class Relay:
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@ -154,7 +167,7 @@ class Relay:
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@kernel
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def init(self):
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self.bus.set_config_mu(
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RELAY_SPI_CONFIG, 16, SPI_DIV, SPI_CS_RELAY | SPI_CS_LED)
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RELAY_SPI_CONFIG, 16, SPIT_RELAY_WR, CS_RELAY | CS_LED)
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@kernel
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def set_led(self, leds: TInt32):
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