forked from M-Labs/artiq
sed: more LaneDistributor comments
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@ -38,22 +38,27 @@ class LaneDistributor(Module):
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o_status_underflow = Signal()
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self.comb += self.cri.o_status.eq(Cat(o_status_wait, o_status_underflow))
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# internal state
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current_lane = Signal(max=lane_count)
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last_coarse_timestamp = Signal(64-glbl_fine_ts_width)
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last_lane_coarse_timestamps = Array(Signal(64-glbl_fine_ts_width)
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for _ in range(lane_count))
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seqn = Signal(seqn_width)
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# The core keeps writing events into the current lane as long as timestamps
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# (after compensation) are strictly increasing, otherwise it switches to
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# the next lane.
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# If spread is enabled, it also switches to the next lane after the current
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# lane has been full, in order to maximize lane utilization.
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# The current lane is called lane "A". The next lane (which may be chosen
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# a later stage by the core) is called lane "B".
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# at a later stage by the core) is called lane "B".
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# Computations for both lanes are prepared in advance to increase performance.
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current_lane = Signal(max=lane_count)
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# The last coarse timestamp received from the CRI, after compensation.
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# Used to determine when to switch lanes.
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last_coarse_timestamp = Signal(64-glbl_fine_ts_width)
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# The last coarse timestamp written to each lane. Used to detect
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# sequence errors.
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last_lane_coarse_timestamps = Array(Signal(64-glbl_fine_ts_width)
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for _ in range(lane_count))
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# Sequence number counter. The sequence number is used to determine which
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# event wins during a replace.
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seqn = Signal(seqn_width)
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# distribute data to lanes
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for lio in self.output:
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self.comb += [
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