From c226aeb0d4f716b2fb4d3e6a73dde09e8e3e7baf Mon Sep 17 00:00:00 2001
From: Robert Jordens <rj@m-labs.hk>
Date: Mon, 29 Feb 2016 14:55:29 +0100
Subject: [PATCH] coredevice/spi: read_sync read bit

---
 artiq/coredevice/spi.py | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/artiq/coredevice/spi.py b/artiq/coredevice/spi.py
index 4145a5513..b75de123c 100644
--- a/artiq/coredevice/spi.py
+++ b/artiq/coredevice/spi.py
@@ -15,6 +15,8 @@ SPI_DATA_ADDR, SPI_XFER_ADDR, SPI_CONFIG_ADDR = range(3)
     SPI_HALF_DUPLEX,
 ) = (1 << i for i in range(8))
 
+SPI_RT2WB_READ = 1 << 2
+
 
 class SPIMaster:
     """Core device Serial Peripheral Interface (SPI) bus master.
@@ -73,7 +75,7 @@ class SPIMaster:
 
     @kernel
     def read_sync(self):
-        r = rt2wb_read_sync(now_mu(), self.channel, SPI_DATA_ADDR,
-                            int(self.ref_period_mu))
+        r = rt2wb_read_sync(now_mu(), self.channel, SPI_DATA_ADDR |
+                            SPI_RT2WB_READ, int(self.ref_period_mu))
         delay_mu(self.ref_period_mu)
         return r