diff --git a/artiq/firmware/libboard_artiq/serwb.rs b/artiq/firmware/libboard_artiq/serwb.rs
index 23a2db391..46fd6e97f 100644
--- a/artiq/firmware/libboard_artiq/serwb.rs
+++ b/artiq/firmware/libboard_artiq/serwb.rs
@@ -16,22 +16,12 @@ fn read_rtm_ident(buf: &mut [u8]) -> &str {
 
 unsafe fn debug_print(rtm: bool) {
     info!("AMC serwb settings:");
-    info!("  delay_min_found: {}", csr::serwb_phy_amc::control_delay_min_found_read());
-    info!("  delay_min: {}", csr::serwb_phy_amc::control_delay_min_read());
-    info!("  delay_max_found: {}", csr::serwb_phy_amc::control_delay_max_found_read());
-    info!("  delay_max: {}", csr::serwb_phy_amc::control_delay_max_read());
-    info!("  delay: {}", csr::serwb_phy_amc::control_delay_read());
     info!("  bitslip: {}", csr::serwb_phy_amc::control_bitslip_read());
     info!("  ready: {}", csr::serwb_phy_amc::control_ready_read());
     info!("  error: {}", csr::serwb_phy_amc::control_error_read());
 
     if rtm {
         info!("RTM serwb settings:");
-        info!("  delay_min_found: {}", csr::serwb_phy_rtm::control_delay_min_found_read());
-        info!("  delay_min: {}", csr::serwb_phy_rtm::control_delay_min_read());
-        info!("  delay_max_found: {}", csr::serwb_phy_rtm::control_delay_max_found_read());
-        info!("  delay_max: {}", csr::serwb_phy_rtm::control_delay_max_read());
-        info!("  delay: {}", csr::serwb_phy_rtm::control_delay_read());
         info!("  bitslip: {}", csr::serwb_phy_rtm::control_bitslip_read());
         info!("  ready: {}", csr::serwb_phy_rtm::control_ready_read());
         info!("  error: {}", csr::serwb_phy_rtm::control_error_read());
diff --git a/artiq/gateware/targets/sayma_amc.py b/artiq/gateware/targets/sayma_amc.py
index 856adb965..fe98c0fac 100755
--- a/artiq/gateware/targets/sayma_amc.py
+++ b/artiq/gateware/targets/sayma_amc.py
@@ -174,7 +174,7 @@ class Standalone(MiniSoC, AMPSoC):
 
         # AMC/RTM serwb
         serwb_pads = platform.request("amc_rtm_serwb")
-        serwb_phy_amc = serwb.phy.SERWBPHY(platform.device, serwb_pads, mode="master")
+        serwb_phy_amc = serwb.genphy.SERWBPHY(serwb_pads, mode="master")
         self.submodules.serwb_phy_amc = serwb_phy_amc
         self.csr_devices.append("serwb_phy_amc")
 
diff --git a/artiq/gateware/targets/sayma_rtm.py b/artiq/gateware/targets/sayma_rtm.py
index 8aecc65ff..16c55c619 100755
--- a/artiq/gateware/targets/sayma_rtm.py
+++ b/artiq/gateware/targets/sayma_rtm.py
@@ -28,6 +28,11 @@ class CRG(Module):
         self.serwb_refclk = Signal()
         self.serwb_reset = Signal()
 
+        serwb_refclk_bufr = Signal()
+        serwb_refclk_bufg = Signal()
+        self.specials += Instance("BUFR", i_I=self.serwb_refclk, o_O=serwb_refclk_bufr)
+        self.specials += Instance("BUFG", i_I=serwb_refclk_bufr, o_O=serwb_refclk_bufg)  
+
         pll_locked = Signal()
         pll_fb = Signal()
         pll_sys4x = Signal()
@@ -37,9 +42,9 @@ class CRG(Module):
                 p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
 
                 # VCO @ 1GHz
-                p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=10.0,
-                p_CLKFBOUT_MULT_F=10, p_DIVCLK_DIVIDE=1,
-                i_CLKIN1=self.serwb_refclk, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb,
+                p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=8.0,
+                p_CLKFBOUT_MULT_F=8, p_DIVCLK_DIVIDE=1,
+                i_CLKIN1=serwb_refclk_bufg, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb,
 
                 # 500MHz
                 p_CLKOUT0_DIVIDE_F=2, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=pll_sys4x,
@@ -145,11 +150,11 @@ class SaymaRTM(Module):
 
         # AMC/RTM serwb
         serwb_pads = platform.request("amc_rtm_serwb")
-        platform.add_period_constraint(serwb_pads.clk_p, 10.)
-        serwb_phy_rtm = serwb.phy.SERWBPHY(platform.device, serwb_pads, mode="slave")
+        platform.add_period_constraint(serwb_pads.clk_p, 8.)
+        serwb_phy_rtm = serwb.genphy.SERWBPHY(serwb_pads, mode="slave")
         self.submodules.serwb_phy_rtm = serwb_phy_rtm
         self.comb += [
-            self.crg.serwb_refclk.eq(serwb_phy_rtm.serdes.refclk),
+            self.crg.serwb_refclk.eq(serwb_phy_rtm.serdes.clocking.refclk),
             self.crg.serwb_reset.eq(serwb_phy_rtm.serdes.reset)
         ]
         csr_devices.append("serwb_phy_rtm")