forked from M-Labs/artiq
sayma_amc/rtm: use new serwb low-speed phy
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parent
913d1e8e12
commit
c18a73d45f
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@ -16,22 +16,12 @@ fn read_rtm_ident(buf: &mut [u8]) -> &str {
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unsafe fn debug_print(rtm: bool) {
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info!("AMC serwb settings:");
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info!(" delay_min_found: {}", csr::serwb_phy_amc::control_delay_min_found_read());
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info!(" delay_min: {}", csr::serwb_phy_amc::control_delay_min_read());
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info!(" delay_max_found: {}", csr::serwb_phy_amc::control_delay_max_found_read());
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info!(" delay_max: {}", csr::serwb_phy_amc::control_delay_max_read());
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info!(" delay: {}", csr::serwb_phy_amc::control_delay_read());
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info!(" bitslip: {}", csr::serwb_phy_amc::control_bitslip_read());
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info!(" ready: {}", csr::serwb_phy_amc::control_ready_read());
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info!(" error: {}", csr::serwb_phy_amc::control_error_read());
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if rtm {
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info!("RTM serwb settings:");
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info!(" delay_min_found: {}", csr::serwb_phy_rtm::control_delay_min_found_read());
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info!(" delay_min: {}", csr::serwb_phy_rtm::control_delay_min_read());
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info!(" delay_max_found: {}", csr::serwb_phy_rtm::control_delay_max_found_read());
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info!(" delay_max: {}", csr::serwb_phy_rtm::control_delay_max_read());
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info!(" delay: {}", csr::serwb_phy_rtm::control_delay_read());
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info!(" bitslip: {}", csr::serwb_phy_rtm::control_bitslip_read());
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info!(" ready: {}", csr::serwb_phy_rtm::control_ready_read());
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info!(" error: {}", csr::serwb_phy_rtm::control_error_read());
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@ -174,7 +174,7 @@ class Standalone(MiniSoC, AMPSoC):
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# AMC/RTM serwb
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serwb_pads = platform.request("amc_rtm_serwb")
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serwb_phy_amc = serwb.phy.SERWBPHY(platform.device, serwb_pads, mode="master")
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serwb_phy_amc = serwb.genphy.SERWBPHY(serwb_pads, mode="master")
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self.submodules.serwb_phy_amc = serwb_phy_amc
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self.csr_devices.append("serwb_phy_amc")
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@ -28,6 +28,11 @@ class CRG(Module):
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self.serwb_refclk = Signal()
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self.serwb_reset = Signal()
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serwb_refclk_bufr = Signal()
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serwb_refclk_bufg = Signal()
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self.specials += Instance("BUFR", i_I=self.serwb_refclk, o_O=serwb_refclk_bufr)
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self.specials += Instance("BUFG", i_I=serwb_refclk_bufr, o_O=serwb_refclk_bufg)
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pll_locked = Signal()
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pll_fb = Signal()
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pll_sys4x = Signal()
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@ -37,9 +42,9 @@ class CRG(Module):
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p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
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# VCO @ 1GHz
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p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=10.0,
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p_CLKFBOUT_MULT_F=10, p_DIVCLK_DIVIDE=1,
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i_CLKIN1=self.serwb_refclk, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb,
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p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=8.0,
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p_CLKFBOUT_MULT_F=8, p_DIVCLK_DIVIDE=1,
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i_CLKIN1=serwb_refclk_bufg, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb,
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# 500MHz
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p_CLKOUT0_DIVIDE_F=2, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=pll_sys4x,
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@ -145,11 +150,11 @@ class SaymaRTM(Module):
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# AMC/RTM serwb
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serwb_pads = platform.request("amc_rtm_serwb")
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platform.add_period_constraint(serwb_pads.clk_p, 10.)
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serwb_phy_rtm = serwb.phy.SERWBPHY(platform.device, serwb_pads, mode="slave")
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platform.add_period_constraint(serwb_pads.clk_p, 8.)
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serwb_phy_rtm = serwb.genphy.SERWBPHY(serwb_pads, mode="slave")
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self.submodules.serwb_phy_rtm = serwb_phy_rtm
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self.comb += [
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self.crg.serwb_refclk.eq(serwb_phy_rtm.serdes.refclk),
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self.crg.serwb_refclk.eq(serwb_phy_rtm.serdes.clocking.refclk),
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self.crg.serwb_reset.eq(serwb_phy_rtm.serdes.reset)
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]
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csr_devices.append("serwb_phy_rtm")
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