forked from M-Labs/artiq
impl offsets. to be tested
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@ -69,6 +69,7 @@ PHASER_DAC_SEL_TEST = 1
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PHASER_HW_REV_VARIANT = 1 << 4
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SERVO_COEFF_WIDTH = 16
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SERVO_DATA_WIDTH = 16
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SERVO_COEFF_SHIFT = 14
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SERVO_T_CYCLE = (32+12+192+24+4)*ns # Must match gateware ADC parameters
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@ -1121,6 +1122,7 @@ class PhaserChannel:
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NORM = 1 << SERVO_COEFF_SHIFT
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COEFF_MAX = 1 << SERVO_COEFF_WIDTH - 1
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DATA_MAX = 1 << SERVO_DATA_WIDTH - 1
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kp *= NORM
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if ki == 0.:
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@ -1146,8 +1148,8 @@ class PhaserChannel:
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b1 >= COEFF_MAX or b1 < -COEFF_MAX):
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raise ValueError("high gains")
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forward_gain = b0 + b1
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effective_offset = y_offset + forward_gain * x_offset
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forward_gain = (b0 + b1) * (DATA_MAX - NORM)
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effective_offset = int(round(DATA_MAX * y_offset + forward_gain * x_offset))
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self.set_iir_mu(profile, b0, b1, a1, effective_offset)
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