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phaser: adjust to new jesd

This commit is contained in:
Robert Jördens 2017-05-22 19:59:53 +02:00
parent 679060af1d
commit bfc224d4ba
1 changed files with 5 additions and 4 deletions
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9
artiq/gateware/targets/phaser.py
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@ -104,10 +104,11 @@ class AD9154JESD(Module, AutoCSR):
for i in range(4): for i in range(4):
phy = JESD204BPhyTX( phy = JESD204BPhyTX(
qpll, platform.request("ad9154_jesd", i), fabric_freq) qpll, platform.request("ad9154_jesd", i), fabric_freq)
phy.gtx.cd_tx.clk.attr.add("keep") phy.transmitter.cd_tx.clk.attr.add("keep")
platform.add_period_constraint(phy.gtx.cd_tx.clk, 40*1e9/linerate) platform.add_period_constraint(phy.transmitter.cd_tx.clk,
40*1e9/linerate)
platform.add_false_path_constraints(self.cd_jesd.clk, platform.add_false_path_constraints(self.cd_jesd.clk,
phy.gtx.cd_tx.clk) phy.transmitter.cd_tx.clk)
self.phys.append(phy) self.phys.append(phy)
to_jesd = ClockDomainsRenamer("jesd") to_jesd = ClockDomainsRenamer("jesd")
self.submodules.core = to_jesd(JESD204BCoreTX(self.phys, settings, self.submodules.core = to_jesd(JESD204BCoreTX(self.phys, settings,
@ -245,7 +246,7 @@ class Phaser(MiniSoC, AMPSoC):
self.crg.cd_sys.clk, self.ad9154.jesd.cd_jesd.clk) self.crg.cd_sys.clk, self.ad9154.jesd.cd_jesd.clk)
for phy in self.ad9154.jesd.phys: for phy in self.ad9154.jesd.phys:
platform.add_false_path_constraints( platform.add_false_path_constraints(
self.crg.cd_sys.clk, phy.gtx.cd_tx.clk) self.crg.cd_sys.clk, phy.transmitter.cd_tx.clk)
def main(): def main():