From bee4902323d79a7b3dd2460fdf3092e06bb33e6c Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sun, 20 Aug 2017 11:47:45 -0400 Subject: [PATCH] add Sayma AMC standalone target --- .../gateware/targets/sayma_amc_standalone.py | 99 +++++++++++++++++++ 1 file changed, 99 insertions(+) create mode 100755 artiq/gateware/targets/sayma_amc_standalone.py diff --git a/artiq/gateware/targets/sayma_amc_standalone.py b/artiq/gateware/targets/sayma_amc_standalone.py new file mode 100755 index 000000000..5370b69a6 --- /dev/null +++ b/artiq/gateware/targets/sayma_amc_standalone.py @@ -0,0 +1,99 @@ +#!/usr/bin/env python3 + +import argparse + +from migen import * + +from misoc.cores import gpio +from misoc.integration.soc_sdram import soc_sdram_args, soc_sdram_argdict +from misoc.integration.builder import builder_args, builder_argdict +from misoc.targets.sayma_amc import MiniSoC + +from artiq.gateware.amp import AMPSoC, build_artiq_soc +from artiq.gateware import rtio +from artiq.gateware.rtio.phy import ttl_simple +from artiq import __version__ as artiq_version + + +class SaymaAMCStandalone(MiniSoC, AMPSoC): + mem_map = { + "cri_con": 0x10000000, + "rtio": 0x20000000, + "rtio_dma": 0x30000000, + "mailbox": 0x70000000 + } + mem_map.update(MiniSoC.mem_map) + + def __init__(self, cpu_type="or1k", **kwargs): + MiniSoC.__init__(self, + cpu_type=cpu_type, + sdram_controller_type="minicon", + l2_size=128*1024, + ident=artiq_version, + ethmac_nrxslots=4, + ethmac_ntxslots=4, + **kwargs) + AMPSoC.__init__(self) + platform = self.platform + platform.toolchain.bitstream_commands.extend([ + "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]", + ]) + + self.submodules.leds = gpio.GPIOOut(Cat( + platform.request("user_led", 0), + platform.request("user_led", 1))) + self.csr_devices.append("leds") + + rtio_channels = [] + for i in (2, 3): + phy = ttl_simple.Output(platform.request("user_led", i)) + self.submodules += phy + rtio_channels.append(rtio.Channel.from_phy(phy)) + + for i in (0, 1): + sma_io = platform.request("sma_io", i) + self.comb += sma_io.direction.eq(1) + phy = ttl_simple.Output(sma_io.level) + self.submodules += phy + rtio_channels.append(rtio.Channel.from_phy(phy)) + + self.config["HAS_RTIO_LOG"] = None + self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels) + rtio_channels.append(rtio.LogChannel()) + + self.clock_domains.cd_rtio = ClockDomain() + self.comb += [ + self.cd_rtio.clk.eq(ClockSignal()), + self.cd_rtio.rst.eq(ResetSignal()) + ] + self.submodules.rtio_core = rtio.Core(rtio_channels) + self.csr_devices.append("rtio_core") + self.submodules.rtio = rtio.KernelInitiator() + self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")( + rtio.DMA(self.get_native_sdram_if())) + self.register_kernel_cpu_csrdevice("rtio") + self.register_kernel_cpu_csrdevice("rtio_dma") + self.submodules.cri_con = rtio.CRIInterconnectShared( + [self.rtio.cri, self.rtio_dma.cri], + [self.rtio_core.cri]) + self.register_kernel_cpu_csrdevice("cri_con") + self.submodules.rtio_moninj = rtio.MonInj(rtio_channels) + self.csr_devices.append("rtio_moninj") + + self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio_core.cri, + self.get_native_sdram_if()) + self.csr_devices.append("rtio_analyzer") + +def main(): + parser = argparse.ArgumentParser( + description="ARTIQ device binary builder / Sayma AMC stand-alone") + builder_args(parser) + soc_sdram_args(parser) + args = parser.parse_args() + + soc = SaymaAMCStandalone(**soc_sdram_argdict(args)) + build_artiq_soc(soc, builder_argdict(args)) + + +if __name__ == "__main__": + main()