forked from M-Labs/artiq
rtiocrg.c: pipistrello also has pll_reset
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e95b06e96d
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bdee914828
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@ -10,9 +10,7 @@ void rtiocrg_init(void)
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char b;
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char b;
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int clk;
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int clk;
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#ifdef CSR_RTIO_CRG_PLL_RESET_ADDR
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rtio_crg_pll_reset_write(0);
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rtio_crg_pll_reset_write(0);
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#endif
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b = 'i';
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b = 'i';
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clk = 0;
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clk = 0;
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fs_read("startup_clock", &b, 1, NULL);
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fs_read("startup_clock", &b, 1, NULL);
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@ -33,11 +31,7 @@ void rtiocrg_init(void)
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int rtiocrg_check(void)
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int rtiocrg_check(void)
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{
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{
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#ifdef CSR_RTIO_CRG_PLL_RESET_ADDR
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return rtio_crg_pll_locked_read();
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return rtio_crg_pll_locked_read();
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#else
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return 1;
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#endif
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}
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}
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int rtiocrg_switch_clock(int clk)
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int rtiocrg_switch_clock(int clk)
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@ -46,22 +40,16 @@ int rtiocrg_switch_clock(int clk)
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current_clk = rtio_crg_clock_sel_read();
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current_clk = rtio_crg_clock_sel_read();
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if(clk == current_clk) {
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if(clk == current_clk) {
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#ifdef CSR_RTIO_CRG_PLL_RESET_ADDR
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busywait_us(150);
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busywait_us(150);
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if(!rtio_crg_pll_locked_read())
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if(!rtio_crg_pll_locked_read())
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return 0;
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return 0;
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#endif
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return 1;
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return 1;
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}
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}
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#ifdef CSR_RTIO_CRG_PLL_RESET_ADDR
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rtio_crg_pll_reset_write(1);
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rtio_crg_pll_reset_write(1);
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#endif
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rtio_crg_clock_sel_write(clk);
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rtio_crg_clock_sel_write(clk);
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#ifdef CSR_RTIO_CRG_PLL_RESET_ADDR
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rtio_crg_pll_reset_write(0);
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rtio_crg_pll_reset_write(0);
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busywait_us(150);
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busywait_us(150);
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if(!rtio_crg_pll_locked_read())
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if(!rtio_crg_pll_locked_read())
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return 0;
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return 0;
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#endif
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return 1;
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return 1;
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}
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}
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